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Book ChapterDOI

Design of Multi-stage CMOS OTA for Low-Power and High Driving Capability

01 Jan 2018-Vol. 469, pp 261-268
TL;DR: In this paper, a three-stage CMOS OTA has been designed in 180 nm technology, which is suitable for low-power applications requiring high driving capability, when both low power and lowvoltage operation are the goals, MOS transistors operating in subthreshold regions are used.
Abstract: Objective/Background: Multi-stage CMOS OTAs have been used in vast areas like micro-sensor nodes, Bio-medical applications. In this paper, a three-stage CMOS OTA has been designed in 180 nm technology, which is suitable for low-power applications requiring high driving capability. Methods/Analysis: When both low-power and low-voltage operation are the goals, MOS transistors operating in subthreshold regions are used. So, in this work, all the transistors of the amplifier operate in subthreshold region. Reversed Nested Miller Compensation (RNMC) technique is used for stabilizing the amplifier. A slew-rate enhancer (SRE) is used to enhance the slew-rate of the amplifier after compensation. Findings: Powered with 1-V supply, the proposed OTA can drive loads up to 450 pF with phasemargin for this maximum load as 45°. The maximum gain achieved is 120 dB for low frequencies. Power dissipation is obtained as 275.39 nW for low capacitive loads (200 pF). Cadence Virtuoso-64 tool is used for simulations. Conclusion/Improvements: The problem with slew-rate at higher frequencies has been found to be not at the final stage but at the first stage and is resolved using the SRE circuit for a stabilized three-stage OTA. The stabilized and slew enhanced amplifier can drive up to 450 pF load with around 4 µW power dissipation.
References
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Journal ArticleDOI
TL;DR: Experimental results have confirmed that, at a minimum supply voltage of 600 mV, lower than the threshold voltage, the topology presents almost rail-to-rail input and output swings and consumes only 550 nW.
Abstract: An ultra-low-voltage ultra-low-power CMOS Miller operational transconductance amplifier (OTA) with rail-to-rail input/output swing is presented The topology is based on combining bulk-driven differential pair and dc level shifters, with the transistors work in weak inversion The improved Miller OTA has been successfully verified in a standard 035-mum CMOS process Experimental results have confirmed that, at a minimum supply voltage of 600 mV, lower than the threshold voltage, the topology presents almost rail-to-rail input and output swings and consumes only 550 nW

186 citations

Journal ArticleDOI
TL;DR: In this article, the nested Miller compensation of three-stage amplifiers is reviewed by using a simple design-oriented approach, which provides stable amplifiers by accurately controlling the overall phase margin as well as that of the internal loop.
Abstract: The nested Miller compensation of three-stage amplifiers is reviewed by using a simple design-oriented approach. The method provides stable amplifiers by accurately controlling the overall phase margin as well as that of the internal loop. Furthermore, the use of nulling resistors to remove the RHP zeros is discussed and optimization criteria are described. A novel technique is presented which allows an amplifier's frequency and settling performance to be greatly improved without increasing power consumption. Thanks to the small compensation capacitors employed, the approach is amenable for integration and in particular where large load capacitors have to be driven. SPICE simulations based on a 0.8-/spl mu/m CMOS design are given and found in remarkable agreement with the theoretical analysis.

145 citations

Journal Article
TL;DR: The reversed nested Miller compensation technique applied to a three-stage operational amplifier is discussed in this paper and new and simple design equations, accurately predicting the loop-gain phase margin, are developed.
Abstract: The reversed nested Miller compensation technique applied to a three-stage operational amplifier is discussed in this paper and new and simple design equations, accurately predicting the loop-gain phase margin, are developed. Techniques for parasitic positive-zero cancellation are also investigated and compared. For this purpose, we found that using nulling resistors is unpractical. Instead, exploiting only one follower (either a voltage or a current one) in the compensation branch results to be more appropriate. Indeed, not only does it avoid any additional constraint on stage transconductance, but it also overcomes the inherent limitations incurred by voltage and current followers when used to compensate two-stage amplifiers. Post-layout simulations on a CMOS opamp using the parameters of a 0.35-/spl mu/m process are found to be in good agreement with the expected results.

110 citations

Journal ArticleDOI
TL;DR: In this paper, the reversed nested Miller compensation technique is applied to a three-stage operational amplifier and new and simple design equations, accurately predicting the loop-gain phase margin, are developed.
Abstract: The reversed nested Miller compensation technique applied to a three-stage operational amplifier is discussed in this paper and new and simple design equations, accurately predicting the loop-gain phase margin, are developed. Techniques for parasitic positive-zero cancellation are also investigated and compared. For this purpose, we found that using nulling resistors is unpractical. Instead, exploiting only one follower (either a voltage or a current one) in the compensation branch results to be more appropriate. Indeed, not only does it avoid any additional constraint on stage transconductance, but it also overcomes the inherent limitations incurred by voltage and current followers when used to compensate two-stage amplifiers. Post-layout simulations on a CMOS opamp using the parameters of a 0.35-/spl mu/m process are found to be in good agreement with the expected results.

96 citations

Journal ArticleDOI
TL;DR: A CMOS OTA in a 0.35- μm technology that occupies only 4.4·10-3 mm2, is powered with a 1-V supply, exhibits 120-dB DC gain and is able to drive a capacitive load up to 200 pF, is designed.
Abstract: A design methodology for three-stage CMOS OTAs operating in the subthreshold region is presented The procedure is focused on the development of ultra-low-power amplifiers requiring low silicon area but being able to drive high capacitive loads Indeed, by following the presented methodology we designed a CMOS OTA in a 035- $\mu{\rm m}$ technology that occupies only $44\cdot 10^{-3}\ {\rm mm}^{2}$ , is powered with a 1-V supply, exhibits 120-dB DC gain and is able to drive a capacitive load up to 200 pF Thanks to proposed methodology, the OTA is able to provide a 20-kHz unity gain bandwidth while consuming 195 nW, even under the high load considered Moreover, the slew rate enhancer circuit in addition to the class AB output stage allows an average slew rate higher than 5 ${\rm mV}/\mu{\rm s}$ with the 200 pF load Comparison with prior art shows an improvement factor in the figures of merit higher than 5

69 citations