Patent
Dopant etch selectivity control
TLDR
In this paper, the etch of two doped silicon portions at two different etch rates is described. And the etches are shown to reduce trapped charges during use and increase the lifespan of flash memory devices.Abstract:
Methods of etching two doped silicon portions at two different etch rates are described. An n-type silicon portion may be etched faster than a p-type silicon portion when both are exposed and present on the same substrate. The n-type silicon portion may be doped with phosphorus and the p-type silicon portion may be doped with boron. In one example, the n-type silicon portion is single crystal silicon and the p-type silicon portion is polycrystalline silicon (a.k.a. polysilicon). The p-type silicon portion may be a polysilicon floating gate in a flash memory cell and may be located above a gate silicon oxide which, in turn, is above an n-type active area single crystal silicon portion. The additional trimming of the n-type active area silicon portion may reduce the accumulation of trapped charges during use and increase the lifespan of flash memory devices.read more
Citations
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References
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Patent
Multiple chamber integrated process system
Dan Maydan,Sasson Somekh,David Nin-Kou Wang,David Cheng,Masato M. Toshima,Isaac Harari,Peter D. Hoppe +6 more
TL;DR: In this paper, an integrated modular multiple chamber vacuum processing system is described, which includes a load lock, may include an external cassette elevator and an internal load lock wafer elevator, and also includes stations about the periphery of the load lock for connecting one, two or several vacuum process chambers to the load-lock chamber.
Patent
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TL;DR: In this paper, a single wafer, semiconductor processing reactor is described, which is capable of thermal CVD, plasmaenhanced CVD and plasma assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing.
Patent
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