Journal ArticleDOI
Easily testable PLA-based finite state machines
Srinivas Devadas,H.-K.T. Ma +1 more
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TLDR
An outline is presented of a synthesis procedure that, beginning from a state transition graph (STG) description of a sequential machine, produces an optimized easily testable programmable logic array (PLA) based logic implementation.Abstract:
An outline is presented of a synthesis procedure that, beginning from a state transition graph (STG) description of a sequential machine, produces an optimized easily testable programmable logic array (PLA) based logic implementation. Previous approaches to synthesizing easily testable sequential machines have concentrated on the stuck-at-fault model; for PLAs, an extended fault model called the crosspoint fault model has been used. The authors propose a procedure of constrained state assignment and logic optimization which guarantees testability for all combinationally irredundant crosspoint faults in a PLA-based finite-state machine. No direct access to the flip-flops is required. The test sequences to detect these faults can be obtained using combinational test generation techniques alone. This procedure thus represents an alternative to a scan design methodology. Results are presented which show that the area/performance penalties in return for easy testability are small. >read more
Citations
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Proceedings ArticleDOI
Redundancies and don't cares in sequential logic synthesis
TL;DR: Preliminary experimental results indicate that by exploiting these don't cares medium-sized irredundant sequential circuits can be synthesized with no area overhead and within reasonable CPU times.
Journal ArticleDOI
Finite state machine synthesis with fault tolerant test function
TL;DR: This work proposes a new method of synthesizing PLA-based finite state machines with fault tolerant test machines by eliminating testing of the test function and shows that the tests generated under the assumption that the entire test function is intact can become invalid.
Journal ArticleDOI
State assignment for hardwired VLSI control units
TL;DR: A comprehensive survey and systematic categorization of the various techniques, in particular, for synchronous sequential circuits with nonmicroprogrammed implementations, for finding a binary encoding of symbolic control states, such that the implementation area of a digital control unit is minimized.
Book ChapterDOI
Evolution of Programmable Logic
TL;DR: The principle of functional decomposition oriented on FPGA chips is analysed in the last part of the chapter and shows particular features of different logic elements and permits to optimize the FSM logic circuits.
Proceedings ArticleDOI
Finite state machine synthesis with fault tolerant test function
TL;DR: A new method of synthesizing programmable logic array (PLA)-based finite-state machines with fault tolerant test machines that allows arbitrary state encoding and guarantees bounded-length test sequences for combinationally irredundant crosspoint faults is proposed.
References
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Proceedings ArticleDOI
A logic design structure for LSI testability
TL;DR: A logic design method that will greatly simplify problems in testing, diagnostics, and field service for LSI is described, based on two concepts that are nearly independent but combine efficiently and effectively.
Journal ArticleDOI
Optimal State Assignment for Finite State Machines
TL;DR: The proposed algorithm for optimal state assignment is based on an innovative strategy: logic minimization of the combinational component of the finite state machine is applied before state encoding, and has been coded in a computer program, KISS, and tested on several examples of finite state machines.
Journal ArticleDOI
MUSTANG: state assignment of finite state machines targeting multilevel logic implementations
TL;DR: The authors present state-assignment algorithms that heuristically maximize the number of common cubes in the encoded network to maximize theNumber of literals in the resulting combinational logic network after multilevel logic optimization.
Journal ArticleDOI
Multi-level logic minimization using implicit don't cares
K. Bartlett,Robert K. Brayton,Gary D. Hachtel,R. Jacoby,C.R. Morrison,R.L. Rudell,Alberto Sangiovanni-Vincentelli,A. Wang +7 more
TL;DR: The authors introduce the concept of R-minimality, which implies minimality with respect to cube reshaping, and demonstrate the crucial role played by this concept in multilevel minimization.