Proceedings ArticleDOI
Extending IP-XACT to embedded system HW/SW integration
TLDR
This paper presents an IP-XACT based design flow that reduces the design time to one third compared to the conventional FPGA flow, the number of automated design phases is doubled and any manual error prone data transfer between HW and SW tools is completely avoided.Abstract:
Typical MPSoC FPGA product design is a rigid waterfall process proceeding one-way from HW to SW design. Any changes to HW trigger the SW project re-creation from the beginning. When several product variations or speculative development time exploration is required, the disk bloats easily with hundreds of Board Support Package (BSP), configuration and SW project files. In this paper, we present an IP-XACT based design flow that solves the problems by agile re-use of HW and SW components, automation and single golden reference source for information. We also present new extensions to IP-XACT since the standard lacks SW related features. Three use cases demonstrate how the BSP is changed, an application is moved to another processor and a function is moved from SW implementation to a HW accelerator. Our flow reduces the design time to one third compared to the conventional FPGA flow, the number of automated design phases is doubled and any manual error prone data transfer between HW and SW tools is completely avoided.read more
Citations
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Journal ArticleDOI
Graph-Grammar-Based IP-Integration (GRIP)—An EDA Tool for Software-Defined SoCs
TL;DR: A novel approach to significantly reduce the design effort to bring-up a working SoC design by automatic IP integration as part of a library-based Software-defined SoC flow is presented.
Proceedings ArticleDOI
IP-XACT for smart systems design: extensions for the integration of functional and extra-functional models
TL;DR: This paper shows how the IP-XACT standard, with some necessary extensions, can effectively support simultaneous simulation of multiple concerns in smart systems, by automatically generating a skeleton of the simulation infrastructure in SystemC.
Proceedings ArticleDOI
Instruction Extension of a RISC-V Processor Modeled with IP-XACT
TL;DR: This work presents an instruction extension flow for a RISC-V processor core modeled in IP-XACT and proposes the workflow to cover adding dedicated hardware in IP -XACT for improved re-usability and design consistency.
Journal ArticleDOI
A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-Chip
Gilberto Ochoa-Ruiz,Pamela Wattebled,Maamar Touiza,Florent de Lamotte,El-Bay Bourennane,Samy Meftali,Jean-Luc Dekeyser,Jean-Philippe Diguet +7 more
TL;DR: A Model Driven Engineering (MDE) methodology for facilitating the modeling of the partial reconfiguration process, and for implementing Dynamic Reconfigurable System-on-Chip (DRSoC) with speedups of 1.5x over other solutions.
Proceedings ArticleDOI
Gamification of System-on-Chip design
Timo Hämäläinen,Erno Salminen +1 more
TL;DR: This paper presents drastic new concepts for SoC design tools that includes 3D visualization and semantic zoom to capture the design content, and gameplay for the design process, so that soC design becomes engaging and users can easier focus on making the essential design decisions.
References
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Proceedings ArticleDOI
Automatic relocation of AUTOSAR components among several ECUs
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