Patent
Fabrication method of bipolar transistor
TLDR
In this paper, the authors used the arsenic implanted polycrystalline silicon for the emitter electrode of NPN transistor to increase the current gain, and for the field-plate of the lateral PNP transistor to reduce the collector-emitter leakage current.Abstract:
Present invention relates to the fabrication method of the bipolar transistor which includes NPN transistor and field-plate lateral PNP transistor. The arsenic implanted polycrystalline silicon is used for the emitter electrode of NPN transistor to increase the current gain, and for the field-plate of the lateral PNP transistor to reduce the collector-emitter leakage current. Also, this polycrystalline silicon is used for the ion implanting mask for the extrinsic base of the NPN transistor and for the emitter, collector of the lateral PNP transistor simultaneously. Therefore, the extrinisc base of NPN transistor and the emitter, collector of the lateral PNP transistor are self-aligned by the polycrystalline silicon, and so one mask is saved by this method.read more
Citations
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Patent
Integrated circuitry having a thin film polysilicon layer in ohmic contact with a conductive layer
TL;DR: In this article, an integrated circuit includes: a semiconductor substrate, a first conductivity type substrate diffusion region within the semiconductor substratum, a thin film polysilicon layer overlying and being in a ohmic electrical connection with the substrate diffusion regions, and a pillar of electrically conductive material extending outwardly from the thin-film poly-silicon (SLP) layer over a diffusion region, the pillar having a total cross-sectional second area where the pillar joins the SLP.
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Self-aligned planar monolithic integrated circuit vertical transistor process
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Patent
Lateral bipolar transistor and method of making the same
Robert K. Cook,Mario M. Pelella +1 more
TL;DR: In this article, a lateral bipolar transistor and a method of making the transistor which is compatible with a method for making MOS transistors to be used in making BICMOS circuits are disclosed.
References
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Patent
Semiconductor integrated circuit
TL;DR: In this article, an inner logic Pwell is positioned on the output terminal side and P diffused regions connected to a power source is positioned at the end of the P-well to prevent latchup.
Patent
Manufacture of semiconductor device
TL;DR: In this paper, the authors proposed a method to inhibit the lateral spreading of Si dioxide layers by a method wherein an oxidation-resistant film having an aperture exposing part of the semiconductor substrate is formed and provided with a chemical Si dioxide layer over the surface; thereafter, an si dioxide layer is formed at the thermal oxide aperture part.
Patent
Process for making a lateral bipolar transistor in a standard CSAG process
TL;DR: In this article, a strip of polysilicon is deposited around a region between the emitter area and collector area on a face of the substrate over said oxide, and then an emitter region having the form of a band enclosing an undiffused central region within the poly-silicon strip and a collector region located outside of the strip are diffused into the tank.
Patent
Method for the manufacture of bipolar transistor structures with self-adjusting emitter and base regions for extreme high frequency circuits
TL;DR: In this paper, a method for the manufacture of bipolar transistor structures with self-adjustable emitter and base regions is described. But the method is not suitable for the case of VLSI circuits.
Patent
Method of manufacturing a semiconductor device
Kazumasa Nawata,Hirokazu Suzuki +1 more
TL;DR: In this paper, a method of manufacturing a semiconductor device for simultaneously forming a plurality of diffused regions of selectively different diffusion depths, comprises forming polycrystalline semiconductor layers of corresponding, selectively different depths on the semiconductor substrate surface provided with a diffusion mask having plurality of diffusion windows.