Journal ArticleDOI
Fault coverage in digital integrated circuits
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In this article, a theoretical expression is derived that evaluates the effectiveness of a set of logic tests for digital integrated circuits and the validity of the proposed figure of merit is examined with experimental data from CMOS integrated circuits.Abstract:
A theoretical expression is derived in this paper that evaluates the effectiveness of a set of logic tests for digital integrated circuits. The validity of the proposed figure of merit is examined with experimental data from CMOS integrated circuits. In addition, the importance of simulating the nonclassical stuck-open/stuck-on CMOS logic faults is also studied.read more
Citations
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Journal ArticleDOI
Defect Level as a Function of Fault Coverage
TL;DR: This correspondence presents a single equation relating the defect level of LSI chips to the yield and stuck-at-fault coverage with some assumptions, and is extended to modules on boards.
Journal ArticleDOI
Fault coverage requirement in production testing of LSI circuits
TL;DR: A technique is described for evaluating the effectiveness of production tests for large scale integrated (LSI) circuit chips based on a model for the distribution of faults on a chip, which implicitly takes into account such variables as fault simulator characteristics, the feature size, and the manufacturing environment.
Proceedings ArticleDOI
Statistical delay fault coverage and defect level for delay faults
TL;DR: A quantitative delay fault Coverage model is discussed to provide a figure of merit for delay testing and a defect-level model is proposed as a function of the yield of a manufacturing process and the statistical delay fault coverage.
Journal ArticleDOI
IC quality and test transparency
Edward J. McCluskey,F. Buelow +1 more
TL;DR: In this article, it is shown that extremely high single-stuck fault coverage is necessary for high quality products and that the dependence of quality on test coverage is linear rather than exponential.
Journal ArticleDOI
Comments on "Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSI"
J.C. Harden,T.E. Mangir +1 more
TL;DR: In this article, the use of redundancy for the yield improvement of VLSI circuits is explored through the use a mathematical model, and it is shown that interconnection density and pattern complexities around each section determines the effectiveness of yield improvement.
References
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Journal ArticleDOI
Probability plotting methods for the analysis of data
M. B. Wilk,R. Gnanadesikan +1 more
TL;DR: This paper describes and discusses graphical techniques, based on the primitive empirical cumulative distribution function and on quantile (Q-Q) plots, percent (P-P) plots and hybrids of these, which are useful in assessing a one-dimensional sample, either from original data or resulting from analysis.
Journal ArticleDOI
Fault modeling and logic simulation of CMOS and MOS integrated circuits
TL;DR: This paper provides a methodology for creating simulator models for tri-state and other dynamic circuit elements that provide for both classical and stuck-open/stuck-on faults, and can be adopted for use on essentially any general purpose logic simulator.
Journal ArticleDOI
Lamp: System description
TL;DR: A general description of the Logic Analyzer for Maintenance Planning (LAMP) system is presented, a digital-logic simulation and analysis system used for logic-design verification, for generation and evaluation of fault-detection and diagnostic tests, and for generation of the trouble-location manual (or fault dictionary) data.