Patent
Finfet devices with unique fin shape and the fabrication thereof
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TLDR
In this article, the authors propose a semiconductor device consisting of a PMOS FinFET and an NMOS fin, where the former contains silicon germanium and the latter contains silicon oxide.Abstract:
A semiconductor device includes a PMOS FinFET and an NMOS FinFET. The PMOS FinFET includes a substrate, a silicon germanium layer disposed over the substrate, a silicon layer disposed over the silicon germanium layer, and a PMOS fin disposed over the silicon layer. The PMOS fin contains silicon germanium. The NMOS FinFET includes the substrate, a silicon germanium oxide layer disposed over the substrate, a silicon oxide layer disposed over the silicon germanium oxide layer, and an NMOS fin disposed over the silicon oxide layer. The NMOS fin contains silicon. The silicon germanium oxide layer and the silicon oxide layer collectively define a concave recess in a horizontal direction. The concave recess is partially disposed below the NMOS fin.read more
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References
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Patent
Semiconductor Devices and Methods of Manufacture Thereof
TL;DR: In this article, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region, which includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide.
Patent
System and methods for converting planar design to FinFET design
Yi-Tang Lin,Lei Cheok-Kei,Shu-Yu Chen,Yu-Ning Chang,Hsiao-Hui Chen,Chih-Sheng Chang,Chien-Wen Chen,Clement Hsingjen Wann +7 more
TL;DR: In this article, a method for generating a layout for a device having FinFETs from a first layout of the device having planar transistors is presented, where the planar layout is analyzed and corresponding Fin-FET structures are generated in a matching fashion.
Patent
Contact Structure of Semiconductor Device
TL;DR: In this paper, the authors describe a contact structure for a semiconductor device consisting of a substrate comprising a major surface and a cavity below the major surface, wherein a strained material in the cavity is different from a lattice constant of the substrate.
Patent
Contact plugs in SRAM cells and the method of forming the same
TL;DR: In this paper, a dielectric layer is formed over a portion of an SRAM cell and a contact plug is formed in the contact opening, where a first mask layer and a second mask layer are formed over the dielectrics layer and patterned.
Patent
Structure and method for finfet integrated with capacitor
Chia-Hsin Hu,Sun-Jay Chang +1 more
TL;DR: In this paper, the authors present an embodiment of a semiconductor structure that includes a first region and a second region; a shallow trench isolation (STI) feature formed in the semiconductor substrate; and a plurality of conductive features disposed on the fin active regions.