Patent
Contact Structure of Semiconductor Device
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TLDR
In this paper, the authors describe a contact structure for a semiconductor device consisting of a substrate comprising a major surface and a cavity below the major surface, wherein a strained material in the cavity is different from a lattice constant of the substrate.Abstract:
The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer.read more
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References
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Journal ArticleDOI
Evidence for strong Fermi-level pinning due to metal-induced gap states at metal/germanium interface
TL;DR: In this article, Ohmic and Schottky properties of metal/germanium (Ge) junction have been investigated and it has been shown that Fermi level at metal/Ge interface is intrinsically pinned at the charge neutrality level (CNL) characterized by the metal-induced gap states model.
Patent
Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
Nick Lindert,Stephen M. Cea +1 more
TL;DR: In this paper, a tri-gate transistor with stained enhanced mobility and its method of fabrication is presented, where a gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and a gate electrode having a pair of laterally opposite sidewalls is formed around and around the gate dieslectric layers.
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Contact resistance reduced p-mos transistors employing ge-rich contact layer
Glenn A. Glass,Anand S. Murthy +1 more
TL;DR: In this paper, techniques for forming transistor devices having reduced parasitic contact resistance relative to conventional devices are described. But these techniques can be implemented using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions.
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Semiconductor device and fabrication method thereof
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High mobility heterojunction complementary field effect transistors and methods thereof
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TL;DR: In this article, a structure and method of fabrication for high performance field effect devices is disclosed, and the MOS structures include a crystalline Si body of one conductivity type, a strained SiGe layer epitaxially grown on the Si body serving as a buried channel for holes, a Si layer encapsulated by Si geysers serving as surface channel for electrons, and a source and a drain containing an epitaxial deposited SiGe of opposing conductivity types than the si body.