Patent
Fully integrated reference circuit having controlled temperature dependence
TLDR
In this paper, the bias voltage of an FET is adjusted to a desired variation characteristic by applying a gate bias voltage having a predetermined variation in value with respect to temperature, which results in the drain current of the FET being substantially constant in terms of temperature.Abstract:
Mobility in an FET is used as a time standard to develop a resistance (or a transconductance or a current) reference which may be fully integrated and which is temperature stable to an arbitrary desired accuracy (or which varies with temperature in a desired fashion). The large temperature dependence of mobility is compensated (or adjusted to a desired variation characteristic) by applying a gate bias voltage having a predetermined variation in value with respect to temperature. In one embodiment the bias voltage of the FET is given a temperature dependence which results in the drain current of the FET being substantially constant with respect to temperature. This current is then used to charge or discharge a capacitor, yielding a precise R-C product which may be implemented fully in integrated form.read more
Citations
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Electronic devices and systems, and methods for making and using the same
TL;DR: In this paper, the Deeply Depleted Channel (DDC) transistors are used to reduce power consumption in devices by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as broader electronics industry to avoid a costly and risky switch to alternative technologies.
Patent
Transistor with threshold voltage set notch and method of fabrication thereof
TL;DR: In this article, the Deeply Depleted Channel (DDC) transistors have been used to tune the threshold voltage of FETs having dopants in the channel region.
Patent
Voltage generator for compensating for temperature dependency of memory cell current
Ken Takeuchi,Tomoharu Tanaka +1 more
TL;DR: In this paper, the gates of the first to fourth MOS transistors are controlled so as to be selectively set into ON/OFF states by the first-to-fourth enable signals and the temperature characteristic is variously adjusted both in the positive and negative directions.
Patent
Low power semiconductor transistor structure and method of fabrication thereof
TL;DR: In this article, a Deeply Depleted Channel (DDC) design is proposed, which allows CMOS based devices to have a reduced σV T compared to conventional bulk CMOS and can allow the threshold voltage V T of FETs having dopants in the channel region to be set much more precisely.
Patent
Temperature compensation circuit
Koji Horie,Minoru Nagata +1 more
TL;DR: In this paper, a temperature compensation circuit includes a bias circuit configured to output a bias current having a current value increasing in proportion to an absolute temperature in a low-temperature region, and having a greater current value than the current value proportional to the absolute temperature, and a transistor which is supplied with the bias current.
References
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Patent
Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
TL;DR: In this paper, a semiconductor integrated circuit (SIC) consists of a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on a chip, and a control circuit on the chip for controlling the power supply circuit.
Patent
Temperature compensated monolithic delay circuit
TL;DR: In this paper, a temperature and processing compensated time delay circuit was proposed, where a bias voltage connected to the gate of the FET (12) varies with temperature in a manner to compensate for the changes in current which flows from the capacitor (14) through the field effect transistor (12), due to changes in temperature.
Patent
Ecl output buffer circuit with improved compensation
TL;DR: An ECL output buffer circuit for generating a stable predetermined output voltage over power supply, temperature and process variations and having a high speed of operation with low power consumption includes a differential pair formed of first and second input transistors (Q102, Q103), an emitter follower transistor (Q101), a first current source (112), and a second current source(114).
Patent
BiCMOS logic gate having linearly operated load FETs
James A. Matthews,Geert Rosseel +1 more
TL;DR: In this paper, a BiCMOS logic circuit utilizes an emitter-coupled pair of bipolar transistors for differentially comparing an input signal with a logic reference level.
Patent
Integrated semiconductor circuit
TL;DR: In this paper, a control loop including a first current source acting as an actual value transmitter for the control loop, and a final control element acting on the first source as a control, is described.