Patent
Generating test sets for diagnosing scan chain failures
TLDR
In this article, software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution are described. But they do not address the problem of scan chain defect detection.Abstract:
Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a “complete” test set—that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.read more
Citations
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Patent
Test pattern generation for diagnosing scan chain failures
TL;DR: In this paper, Wu et al. described techniques that can be used to generate scan chain test patterns and improve scan chain failure diagnosis resolution, which can be applied to locate faults over multiple capture cycles in the scan chain.
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Cell-aware fault model creation and pattern generation
Friedrich Hapke,Rene Krenz-Baath,A. Glowatz,Juergen Schloeffel,Peter Weseloh,Michael Wittke,Mark Kassab,Christopher W. Schuermyer +7 more
TL;DR: In this article, the authors proposed a cell-aware fault model to address layout-based intra-cell defects by performing analog simulations on the transistor-level netlist of a library cell and then by library view synthesis.
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Protection of proprietary embedded instruments
Alfred L. Crouch,John C. Potter +1 more
TL;DR: In this article, the authors propose a data path segmentation protocol for a network of storage units. But they do not address the problem of the gateway storage unit not storing a gateway value and the key signal not being transmitted to the gateway.
Patent
Two-Dimensional Scan Architecture
TL;DR: In this article, a two-dimensional scan cell network is constructed by coupling input for each scan cell to outputs for two or more other scan cells and/or primary inputs through a multiplexer.
Patent
Fault location estimation device, fault location estimation method, and program
TL;DR: In this article, a faulty scan chain identification unit is used to identify a faulty chain and its fault type based on result of operation verification test, and a path trace narrowing unit that references logic circuit configuration information, signal line expected value, a failure-observed scan FF, and test result of a defective circuit to extract a scan FF on the faulty chain, which may be reached from a failure observed on a normal scan chain by tracing back a failure propagation path while performing implication procedure for an input side, and thereby further narrows the faulty scan FF narrowing unit.
References
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Proceedings ArticleDOI
Embedded deterministic test for low cost manufacturing test
Janusz Rajski,Jerzy Tyszer,M. Kassab,Nilanjan Mukherjee,Rob Thompson,Kun-Han Tsai,A. Hertwig,Nagesh Tamarapalli,Grzegorz Mrugalski,Geir Eide,Jun Qian +10 more
TL;DR: Embedded deterministic test technology is introduced, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time.
Journal ArticleDOI
Controllability/observability analysis of digital circuits
TL;DR: The testability of a digital circuit is directly related to the difficulty of controlling and observing the logical values of internal nodes from circuit inputs and outputs, respectively as mentioned in this paper, and the testability is also related to how well the internal nodes can be controlled and observed.
Proceedings ArticleDOI
A technique for fault diagnosis of defects in scan chains
TL;DR: The proposed technique handles both stuck-at and timing failures (transition faults and hold time faults) and improves the diagnostic resolution by ranking the suspect scan cells inside a range of scan cells.
Proceedings ArticleDOI
Diagnosis of scan path failures
S. Edirisooriya,G. Edirisooriya +1 more
TL;DR: This work proposes a simple extension to the scan chain to diagnose faults in scan chains, which is likely to occupy nearly 30% of a chip area and hence warrants consideration during fault diagnosis.
Proceedings ArticleDOI
An efficient scheme to diagnose scan chains
S. Narayanan,A. Das +1 more
TL;DR: A novel strategy to efficiently diagnose a scan chain is presented, to add circuitry to a scan flop to enable its scan-out port to be either set or reset.
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