High speed latch and flip-flop

TLDR: In this paper, a latch and flip-flop are disclosed that have a reduced clock-to-q delay and/or a reduced setup time, where the data input signal is passed directly to a data output terminal, and the complement data input signals are passed direct to a complement data output signal.

Abstract: A latch and flip-flop are disclosed that have a reduced clock-to-q delay and/or a reduced setup time. This is preferably accomplished by providing both a data input signal and a complement data input signal to the latch or flip-flop. The data input signal and the complement data input signal are selectively connected to opposite sides of a pair of cross-coupled gates (409, 410) via a switch or the like. The switch is preferably controlled by an enable signal, such as a clock. With the switch elements enabled, the data input signal is passed directly to a data output terminal, and the complement data input signal is passed directly to a complement data output signal. Because the data input signal is passed directly to a data output terminal, and the complement data input signal is passed directly to a complement data output signal, the clock-to-q time may be reduced. In addition, because the data input signal and the complement data input signal drive opposite sides of the cross-coupled pair of gates, the state of the cross-coupled pair of gates can be more quickly set to a desired state. This helps reduce the clock-to-q time, as well as the setup time.