Journal ArticleDOI
High-Speed Monolithic Multipliers for Real-Time Digital Signal Processing
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TLDR
Real-time digital signal processing requires very fast multiplication, which is now becoming possible using mathematical techniques to take advantage of single-chip multipliers.Abstract:
Real-time digital signal processing requires very fast multiplication, which is now becoming possible using mathematical techniques to take advantage of single-chip multipliers.read more
Citations
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Journal ArticleDOI
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
TL;DR: Since the multiplier has a regular cellular array structure similar to an array multiplier, it is suitable for VLSI implementation and is excellent in both computation speed and regularity in layout.
Journal ArticleDOI
A fast parallel multiplier-accumulator using the modified Booth algorithm
TL;DR: A dependence graph (DG) is presented to visualize and describe a merged multiply-accumulate (MAC) hardware that is based on the modified Booth algorithm, in which an accurate delay model for deep submicron CMOS technology is used.
Journal ArticleDOI
The Design of Easily Testable VLSI Array Multipliers
TL;DR: The testability of two well-known array multiplier structures is studied in detail and it is shown that, with appropriate cell design, array multipliers can be designed to be very easily testable.
Patent
AN XxY BIT ARRAY MULTIPLIER/ACCUMULATOR CIRCUIT
TL;DR: In this article, a modified Booth's algorithm is implemented with an array structure which maintains a regular and systematic structure, using adders and multiplexers in a predetermined column and row arrangement.
Journal ArticleDOI
A Fast Serial-Parallel Binary Multiplier
TL;DR: A fast serial-parallel (FSP) multiplier design derived from the carry-save add-shift (CSAS) multiplier structure is modified so that it operates as a CSAS unit for the first n clocks and reconfigures itself as an n bit ripple-carry parallel adder at the (n + 1)st clock, thus allowing the carries to ripple through.
References
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Journal ArticleDOI
A Suggestion for a Fast Multiplier
TL;DR: A design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step, using straightforward diode-transistor logic.
Journal ArticleDOI
High-Speed Arithmetic in Binary Computers
TL;DR: Methods of obtaining high speed in addition, multiplication, and division in parallel binary computers are described and then compared with each other as to efficiency of operation and cost.
Journal ArticleDOI
A Suggestion for a Fast Multiplier
TL;DR: The author develops an adder tree to sum this set when t= 1 the maximum number of regions intersections of n t-flats and shows that a tree will be dependent on both t and n.
Journal ArticleDOI
A Proof of the Modified Booth's Algorithm for Multiplication
TL;DR: A simplified proof of a modification of Booth's multiplication algorithm by MacSorley to a form which examines three multiplier bits at a time is presented.