iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Text Line Extraction

TLDR: iDocChip is a low power, energy-efficient accelerator with real-time capabilities called iDocChip, which is a hybrid hardware-software programmable System-on-Chip (SoC) for digitizing historical documents, and the resulting custom hardware accelerator outperforms the existing anyOCR software implementation by 120x, while achieving 1700x higher energy efficiency without affecting the high accuracy of the system.

Abstract: Digitizing historical archives poses a great challenge due to the quality degradation existing in these documents. Hence, even well-established Optical Character Recognition (OCR) systems, such as Abby, OCRopus, Tesseract, etc., fail to give sufficient recognition accuracy for historical archives, since they are optimized for transcribing contemporary documents. In contrast, the open-source anyOCR system is designed specifically for digitizing historical documents with state-of-the-art image processing techniques, to achieve high accuracy. Nowadays, the retrieval of historical document images for further OCR requires special scanning devices that are bulky and stationary. As a result, a portable device that combines scanning and OCR capabilities is beneficial to transcribe documents without the need to remove them from where they are archived. For example, smart goggles equipped with embedded OCR device can be used for instant word spotting. However, the available anyOCR software implementation has long runtime and high power consumption. As a solution, we propose a low power, energy-efficient accelerator with real-time capabilities called iDocChip, which is a hybrid hardware-software programmable System-on-Chip (SoC) for digitizing historical documents. This chip can be easily integrated in a portable device. This paper focuses on one of the most crucial processing steps in anyOCR: Text line extraction. We propose, to the best of our knowledge, the first hybrid hardware-software architecture of the text line extraction technique implemented on an FPGA based programmable SoC. The resulting custom hardware accelerator outperforms the existing anyOCR software implementation by 120x, while achieving 1700x higher energy efficiency without affecting the high accuracy of the system.