Proceedings ArticleDOI
Low power divider using vedic mathematics
Dalal Rutwik Kishor,V. S. Kanchana Bhaaskaran +1 more
- pp 575-580
TLDR
The validated designs were implemented using industry standard Cadence® software using 45nm technology library and show appreciable reduction in circuit latency and in Look-Up-Table (LUT) utilization using proposed Vedic divider than the conventional divider.Abstract:
Divider is an inevitable and basic hardware module employed in advanced and high speed digital signal processing (DSP) units of high precision. It is widely used in radar technology, communication, industrial control systems and linear predictive coding (LPC) algorithms in speech processing. This paper proposes a fast, low power and cost effective architecture of a divider using the ancient Indian Vedic division algorithm. The merits of the proposed architecture are proved by comparing the gate count, power consumption and delay against the conventional divider architectures. The validation of the proposed architecture has resulted in 52.93 percent reduction in power dissipation against comparison with conventional divider using repeated subtraction. The designs were implemented using industry standard Cadence® software using 45nm technology library. The design has been validated on FPGA Spartan-3E kit. The validation results show appreciable reduction in circuit latency and in Look-Up-Table (LUT) utilization using proposed Vedic divider than the conventional divider.read more
Citations
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Proceedings ArticleDOI
Design of Approximate Dividers for Error Tolerant Applications
TL;DR: This paper explores architectural designs of approximate unsigned integer dividers based on restoring and non-restoring algorithms as the subtractor cell is the basic building of a divider and the approximate restoring dividers are performing superior to non-Restoring dividers both in-terms of design parameters and error metrics.
Proceedings ArticleDOI
Design Of High Performance Digital Divider
Karan Kataria,Sunil Patel +1 more
TL;DR: Computation using Vedic mathematics decreases considerable extent of iterations resulted in minimized delay and power compared to the mostly used non – Vedic architectures.
Proceedings ArticleDOI
Division operation based on Vedic mathematics
TL;DR: The proposed work focuses on division operation which is an important operation in areas such as image processing, networking, signal processing, computer graphics, numerical application, scientific applications and in processor implementation.
Proceedings ArticleDOI
Low latency divider using ensemble of moving average curves
TL;DR: This paper proposes a fixed-point divider based on an ensemble of moving average (EnMA) curves that guaranteed 13-bit precision in division and can be effectively used for image processing applications.
Journal ArticleDOI
Performance analysis of Vedic mathematics algorithms on re-configurable hardware platform
Rhea Biji,Vijay Savani +1 more
TL;DR: It has been observed that the Vedic algorithms operate faster, consume less power, and occupy less area on a targeted hardware platform.
References
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Advances in Computing, Communications and Informatics (ICACCI)
Sabu M. Thampi,Michal Wozniak,Oge Marques,Dilip Krishnaswamy,Christian Callegari,Hideyuki Takagi,Zoran Bojkovic,Neeli R. Prasad,Jose M. Alcaraz Calero,Joel J. P. C. Rodrigues,Natarajan Meghanathan,Ravi Sandhu +11 more
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TL;DR: A class of iterative integer division algorithms is presented based on look-up table and Taylor-series approximations to the reciprocal, which naturally produce an exact remainder, which is very useful for implementing precise rounding specifications.
Proceedings ArticleDOI
Novel binary divider architecture for high speed VLSI applications
TL;DR: Novel Binary divider architecture for high speed VLSI application using such ancient methodology using Boolean logic with ancient Vedic mathematics resulted in substantial amount of iteration being eliminated that resulted in ~46% reduction in delay and ~27% reduced in power compared with the mostly used (Repetitive subtraction method).
Journal ArticleDOI
Design of a fast radix-4 SRT divider and its VLSI implementation
C.-L. Wey,C.-P. Wang +1 more
TL;DR: This paper presents a fast radix-4 SRT division architecture that takes 247 ns for a double precision division (56 bits for fraction part), where the 2 /spl mu/m CMOS technology in MAGIC is employed and simulated.
Proceedings ArticleDOI
Revisiting SRT quotient digit selection
TL;DR: This work presents expressions for the number of bits needed for the truncated remainder and divisor, thus eliminating the need for a search through the truncation parameter space for validation, and presents simple algorithms to properly map truncated negative divisors and remainders into nonnegative values.
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