Patent
Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
Veena Misra,Suresh Venkatesan,Christopher C. Hobbs,B. Smith,Jeffrey S. Cope,Earnest B. Wilson +5 more
Abstract:
A method for forming a metal gate MOS transistor begins by forming source and drain electrodes (26, 28, and/or 118) within a substrate (12 or 102). These source and drain regions (26, 28, and 118) are self-aligned to a lithographically-patterned feature (24 or 108). After formation of the source and drain regions, the features (24 and 108 are processed to fill these features with a metallic gate layer (28a or 128a). This metal layer (28a or 128a) is then chemically mechanically polished (CMPed) to form a metallic plug region (28b or 128b) within the features (24 or 108). The plug region (28b or 128b) is formed in either an inlaid or dual inlaid manner wherein this metallic plug region (28b or 128b) is self-aligned to the previously formed source and drain regions and preferably functions as a metal MOS gate region.read more
Citations
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Patent
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TL;DR: In this paper, a method of forming a metal gate structure, on a high k gate insulator layer, for NMOS devices, and simultaneously creating a metal-polysilicon gate structure on the same high-k gate insulators for PMOS devices has been developed.
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References
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Patent
Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps
TL;DR: In this article, a sub-micron FET is disclosed made by a method using expendable self-aligned gate structure up to and including the step of annealing the source/drain regions.
Patent
Inverted spacer transistor
Robert S. Chau,Chan-Hong Chern,Shahriar Ahmed,Robert F. Hainsey,Robert J. Stoner,Todd Wilke,Leopoldo D. Yau +6 more
TL;DR: In this paper, a gate dielectric is formed between the spacers at the bottom of the trench on the semiconductor substrate, which is then filled with a gate electrode material which is chemically-mechanically polished back to isolate the gate electrode within the trench, and the first layer is removed leaving the gate dieelectric, gate electrode and spacers behind.
Patent
Insulated-gate field-effect transistor structure and method
TL;DR: In this article, an insulated gate field effect transistor (IGFET) is formed on a semiconductor substrate and an insulating layer 50 is formed over a channel region 28 which separates the source 12 and drain 20, and also over the overlapped portions of the source 18 and drain 26.
Patent
Method for making a semiconductor device comprising a dual metal gate using a chemical mechanical polish
TL;DR: In this article, a method of manufacturing a semiconductor device gate that reduces gate length variability while maintaining self-alignment and eliminating etch damage and substrate contamination is provided, where a gate opening is formed in an oxide layer (16) using anisotropic etch.
Patent
Method for forming a compact transistor structure
TL;DR: In this paper, a vertically raised transistor (10) is formed having a substrate (12), a conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor, and a first doped region (16a and 16b) and a second doped regions (16b) are each electrically coupled to the conductively plug region via sidewall contacts.