Patent
Method of fabricating a field-effect transistor utilizing an SOI substrate
TLDR
In this paper, a gate oxide film is formed on an exposed surface of the SOI layer inside the opening, and side walls are formed on side surfaces of the gate electrode, and a silicide film is created on the gate electrodes and the source and drain regions.Abstract:
To form a recess defining a channel region in a SOI layer, a LOCOS oxide film is formed on a surface of the SO layer and then removed. Then, side walls of CVD oxide is formed on side surfaces defining an opening of a LOCOS oxide restraining film. Then, a gate oxide film is formed on an exposed surface of the SOI layer inside the opening. Then, CVD polycrystalline silicon is formed on the whole wafer surface, and then etched back to form a gate electrode of polycrystalline silicon inside the opening. At this time, a top surface of the gate electrode is at a level lower than a top surface of the restraining film. Next, the restraining film and the side walls are removed and ion implantation into the SOI layer is performed using the gate electrode as a mask to thereby form a source and a drain region. Then, side walls are formed on side surfaces of the gate electrode, and a silicide film is formed on the gate electrode and the source and drain regions.read more
Citations
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Patent
Semiconductor device structures and methods of forming semiconductor structures
Justin Brask,Jack T. Kavalieros,Brian S. Doyle,Uday Shah,Suman Datta,Amlan Majumdar,Robert S. Chau +6 more
TL;DR: In this article, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal planes is denser than the second crystal planes and wherein the hard mask was formed on the second plane.
Patent
Field effect transistor with narrow bandgap source and drain regions and method of fabrication
TL;DR: In this article, a transistor having a narrow bandgap semiconductor source/drain region is described, which includes a gate electrode formed on a gate dielectric layer formed on silicon layer.
Patent
Method of forming a fully-depleted soi (silicon-on-insulator) mosfet having a thinned channel region
TL;DR: In this article, a sub-0.05 μm channel length fully-depleted SOI MOSFET device with low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided.
Patent
Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOS
TL;DR: In this paper, a high-performance recessed channel CMOS device including an SOI layer having a recessed channels region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layers and a method for fabricating the same are provided.
Patent
Method for fabricating transistor with thinned channel
Justin K. Brask,Robert S. Chau,Suman Datta,Mark L. Doczy,Brian S. Doyle,Jack T. Kavalieros,Amlan Majumdar,Matthew V. Metz,Marko Radosavljevic +8 more
TL;DR: A method of fabricating a MOS transistor having a thinned channel region is described in this paper, where the channel region was etched following removal of a dummy gate and the source and drain regions have relatively low resistance with the process.
References
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Patent
Process for fabricating a fully self-aligned soi mosfet
TL;DR: In this paper, a planarization process is carried out to form a gate electrode (36) in the recess, and source and drain regions (40, 42) are formed in a self-aligned manner to the gate electrode.
Patent
Process for forming silicon on insulator devices having elevated source and drain regions
TL;DR: In this paper, a dielectric layer is formed over an SOI layer and then masked and etched to define a trench, and the sidewalls of the trench are thermally oxidized to form a layer of oxide thereon.
Patent
Local thinning of channel region for ultra-thin film SOI MOSFET with elevated source/drain
TL;DR: In this paper, an elevated source/drain structure is described in which the channel region is thinned by local oxidation and wet etch while the source and drain region remained thick.
Patent
Fabrication method for a semiconductor device on a semiconductor on insulator substrate using a two stage threshold adjust implant
TL;DR: In this article, a threshold adjust implantation process is performed after field oxidation to avoid the effects of dopant redistribution and segregation, which results in the reduction of edge leakage and threshold voltage sensitivity to device layer thickness.
Patent
Method for producing a silicon technology transistor on a nonconductor
TL;DR: In this article, the authors present a method for producing a silicon technology transistor on a non-conductor, which consists in particular of forming a thin film of silicon (6) on nonconductor (4) and then a mask (8, 10) including one opening (13) at the location provided for the channel of the transistor; locally oxidizing (14) the unmasked silicon to form an oxidation film; eliminating the mask; forming source (18, and drain (20) regions in the silicon by ion implantation with the oxidation film being used to mask