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Thomas S. Kanarsky
Researcher at IBM
Publications - 47
Citations - 1987
Thomas S. Kanarsky is an academic researcher from IBM. The author has contributed to research in topics: Silicon on insulator & Layer (electronics). The author has an hindex of 24, co-authored 47 publications receiving 1973 citations.
Papers
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Journal ArticleDOI
Extension and source/drain design for high-performance FinFET devices
J. Kedzierski,Meikei Ieong,E.J. Nowak,Thomas S. Kanarsky,Ying Zhang,Ronnen Andrew Roy,Diane C. Boyd,David M. Fried,Hon-Sum Philip Wong +8 more
TL;DR: In this article, double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm, with particular attention given to minimizing the parasitic series resistance.
Proceedings ArticleDOI
Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs
Kern Rim,Jack O. Chu,Huajie Chen,Keith A. Jenkins,Thomas S. Kanarsky,Kam-Leung Lee,Anda Mocuta,Huilong Zhu,Ronnen Andrew Roy,J. Newbury,John A. Ott,K. Petrarca,Patricia M. Mooney,D. Lacey,Steven J. Koester,Kevin K. Chan,Diane C. Boyd,Meikei Ieong,Hon-Sum Philip Wong +18 more
TL;DR: In this article, current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFets with well-controlled threshold voltage V/sub T/ and overlap capacitance C/sub OV/ characteristics for L/sub poly/ and L/ sub eff/ below 80 nm and 60 nm.
Patent
Hybrid planar and FinFET CMOS devices
TL;DR: In this paper, a planar single gated FET and a FinFET are placed on the same SOI substrate, and resist imaging and a patterned hard mask are used in trimming the width of the active device region.
Proceedings ArticleDOI
High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices
J. Kedzierski,David M. Fried,Edward J. Nowak,Thomas S. Kanarsky,Jed H. Rankin,Hussein I. Hanafi,Wesley C. Natzle,Diane C. Boyd,Ying Zhang,Ronnen Andrew Roy,J. Newbury,Chienfan Yu,Qingyun Yang,P. Saunders,C.P. Willets,A.P. Johnson,S.P. Cole,H.E. Young,N. Carpenter,D. Rakowski,Beth Ann Rainey,Peter E. Cottrell,Meikei Ieong,Hon-Sum P. Wong +23 more
TL;DR: In this article, double-gate FinFET devices with asymmetric and symmetric polysilicon gates have been fabricated and shown to have drain currents competitive with fully optimized bulk silicon technologies.
Patent
Method and process to make multiple-threshold metal gates CMOS technology
Amos Ricky,Katayun Barmak,Diane C. Boyd,Cyril Cabral,Meikei Leong,Thomas S. Kanarsky,J. Kedzierski +6 more
TL;DR: In this paper, a method of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable is provided and total salicidation with a metal bilayer or metal alloy is provided.