Diane C. Boyd

TL;DR: In this article, double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm, with particular attention given to minimizing the parasitic series resistance.

TL;DR: In this paper, a novel structure and technology has been developed for high performance CMOS using hybrid silicon substrates with different crystal orientations (namely pFET on [110]-oriented surface and nFETs on (100) surface) through wafer bonding and selective epitaxy devices with physical gate oxide thickness of 12 nm.

TL;DR: In this article, current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFets with well-controlled threshold voltage V/sub T/ and overlap capacitance C/sub OV/ characteristics for L/sub poly/ and L/ sub eff/ below 80 nm and 60 nm.

TL;DR: In this paper, a planar single gated FET and a FinFET are placed on the same SOI substrate, and resist imaging and a patterned hard mask are used in trimming the width of the active device region.

TL;DR: In this article, a tensile-strained Si layer was transferred to form an ultra-thin (<20 nm) strained Si directly on insulator (SSDOI) structure and electron and hole mobility enhancements were demonstrated.