Patent
Methods and apparatus for extracting parasitic capacitance values from a physical design of an integrated circuit
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TLDR
In this article, computer-implemented methods and apparatus for extracting and computing parasitic capacitance values and capacitances respectively, from a physical design of an integrated circuit are described.Abstract:
Computer-implemented methods and apparatus for extracting and computing parasitic capacitance values and capacitances respectively, from a physical design of an integrated circuit are described. In one embodiment, the physical design comprises a plurality of layered conductors which are disposed within a first dielectric material. At least one conductor of the plurality of conductors is identified, and for the identified conductor, the first dielectric material is replaced for calculational purposes with a second (fictitious) dielectric material having a dielectric constant which is higher than the dielectric constant of the replaced dielectric material. In general, the second dielectric may have a different dielectric constant for each identified layer or elevation. Parasitic capacitance values are then computed for the integrated circuit. In a preferred embodiment, spaced-apart conductors at a common substrate elevation are identified, and a distance between the conductors is determined. If the determined distance exceeds a predetermined distance value, the first dielectric material is replaced with the second dielectric material. Such provides a basis for extracting parasitic capacitance values and computing one or more parasitic capacitances which more accurately represents the effect of the presence of fill structures within the physical integrated circuit.read more
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