Patent
Methods and apparatus for performing statistical static timing analysis
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TLDR
In this article, a method and an apparatus to perform static static timing analysis have been described, which includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners.Abstract:
A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners using a static timing analysis module, and estimating performance of the circuit at a predetermined confidence level based on results of the statistical analysis during an automated design flow of the circuit without using libraries at the predetermined confidence level.read more
Citations
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References
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Proceedings ArticleDOI
First-order incremental block-based statistical timing analysis
TL;DR: In this article, a canonical first order delay model is proposed to propagate timing quantities like arrival times and required arrival times through the timing graph in this canonical form and the sensitivities of all timing quantities to each of the sources of variation are available.
Proceedings ArticleDOI
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
TL;DR: An efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay while incorporating the effects of spatial correlations of intra-die parametervariations, using a method based on principal component analysis.
Patent
Systems, methods, and apparatus to perform statistical static timing analysis
TL;DR: In this article, a method and an apparatus to perform static static timing analysis have been described, which includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners.
Patent
Method for correcting a mask design layout
TL;DR: In this article, a method for performing a mask design layout resolution enhancement includes determining a level of correction for the design layout for a predetermined parametric yield with a minimum total total correction cost.
Journal ArticleDOI
Statistical timing analysis using bounds and selective enumeration
TL;DR: This paper provides a formal definition of the statistical delay of a circuit and derive a statistical timing analysis method from this definition, and proposes a new method for computing statistical bounds which has linear run time complexity.