Patent
Methods for forming high-performing dual-damascene interconnect structures
TLDR
In this paper, a dual damascene method and structures for IC interconnects which use a dual-damascene process incorporating a low-k dielectric material, high conductivity metal, and an improved hard mask scheme are provided.Abstract:
Dual damascene methods and structures are provided for IC interconnects which use a dual-damascene process incorporating a low-k dielectric material, high conductivity metal, and an improved hard mask scheme. A pair of hard masks are employed: a silicon dioxide layer and a silicon nitride layer, wherein the silicon dioxide layer acts to protect the silicon nitride layer during dual damascene etch processing, but is subsequently sacrificed during CMP, allowing the silicon nitride layer to act as a the CMP hard mask. In this way, delamination of the low-k material is prevented, and any copper-contaminated silicon dioxide material is removed.read more
Citations
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Patent
Top layers of metal for high performance IC's
TL;DR: In this paper, a method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the wafer was proposed, where electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
Patent
Method of depositing dielectric materials in damascene applications
Ju-hyung Lee,Ping Xu,Shankar Venkataraman,Li-Qun Xia,Fei Han,Ellie Yieh,Srinivas D. Nemani,Kangsub Yim,Farhad Moghadam,Ashok Sinha,Yi Zheng +10 more
TL;DR: In this paper, a method for depositing an oxygen-doped dielectric layer may be used for a barrier layer or a hardmask, which is used as a barrier in damascene or dual damascenes applications.
Patent
Process for selectively etching dielectric layers
TL;DR: In this paper, a method for etching a dielectric structure is provided for dual damascene structures using a plasma source gas that comprises nitrogen atoms and fluorine atoms.
Patent
Two-layer film for next generation damascene barrier application with good oxidation resistance
TL;DR: In this article, a method for processing a substrate including providing a processing gas comprising an organosilicon compound comprising a phenyl group to the processing chamber, and reacting the processing gas to deposit a low k silicon carbide barrier layer useful as a barrier layer in Damascene or dual damascene applications with low k dielectric materials.
Patent
Dual damascene structure and method
Kaushik A. Kumar,Douglas C. La Tulipe,Timothy J. Dalton,Larry Clevenger,Andy Cowley,Erdem Kaltalioglu,Jochen Schacht +6 more
TL;DR: In this article, a dual damascene structure and method of fabrication of semiconductor wafer wafer processing chamber is presented, and a method of cleaning a semiconductor processing chamber while a wafer remains residing within the chamber is discussed.
References
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Patent
Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
Melanie Min-Chieh Chow,John Edward Cronin,William Leslie Guthrie,Carter Welling Kaanta,Barbara Jean Luther,William John Patrick,Kathleen Alice Perry,Charles L. Standley +7 more
TL;DR: In this article, a planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established, and the first layer then is covered by an etch stop material.
Patent
Process for forming a semiconductor device
TL;DR: In this article, a process for forming a semiconductor device is described in which an insulating layer is nitrided and then covered by a thin adhesion layer before depositing a composite copper layer.
Patent
Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC)
Ajay Jain,Kevin D. Lucas +1 more
TL;DR: In this paper, an anti-reflective Ta3 N5 coating was used as an etch stop and barrier layer in a dual damascene structure and for I line or G line lithography.
Patent
Method of making a damascene metallization
TL;DR: In this article, a semiconductor process and structure is provided for use in single or dual damascene metallization processes, where a thin metal layer which serves as an etch stop and masking layer is deposited upon a first dielectric layer.
Patent
Semiconductor structure having multiple levels of self-aligned interconnection metallization, and methods for its preparation
TL;DR: In this paper, an improved semiconductor structure is disclosed, including at least one stud-up and an interconnection line connected thereto, wherein the stud-ups and interconnection lines are formed from a single layer of metal.