Patent
Top layers of metal for high performance IC's
TLDR
In this paper, a method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the wafer was proposed, where electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.Abstract:
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.read more
Citations
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References
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Proceedings ArticleDOI
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
Kaizad Mistry,C. Allen,C. Auth,B. Beattie,Daniel B. Bergstrom,M. Bost,M. Brazier,M. Buehler,Annalisa Cappellani,R. Chau,C. H. Choi,G. Ding,K. Fischer,Tahir Ghani,R. Grover,W. Han,D. Hanken,M. Hattendorf,J. He,J. Hicks,R. Huessner,D. Ingerly,Pulkit Jain,R. James,L. Jong,Subhash M. Joshi,C. Kenyon,K. Kuhn,K. Lee,Huichu Liu,J. Maiz,B. Mclntyre,P. Moon,J. Neirynck,S. Pae,C. Parker,D. Parsons,Chetan Prasad,L. Pipes,M. Prince,Pushkar Ranade,T. Reynolds,J. Sandford,Lucian Shifren,J. Sebastian,J. Seiple,D. Simon,Swaminathan Sivakumar,Pete Smith,C. Thomas,T. Troeger,P. Vandervoorn,S. Williams,K. Zawadzki +53 more
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Patent
Plated copper interconnect structure
Chiu Ting,Valery M. Dubin +1 more
TL;DR: In this article, a high conductivity interconnect structure is formed by electroplating or electroless plating of Cu or a Cu-base alloy on a seed layer comprising an alloy of a catalytically active metal such as Cu, and a refractory metal, such as Ta.
Proceedings ArticleDOI
Full copper wiring in a sub-0.25 /spl mu/m CMOS ULSI technology
Daniel C. Edelstein,John E. Heidenreich,Ronald D. Goldblatt,William J. Cote,Cyprian E. Uzoh,Naftali E. Lustig,Peter Roper,Thomas L. McDevitt,W. Motsiff,A. Simon,J. Dukovic,Richard A. Wachnik,H. Rathore,R. Schulz,L. Su,Stephen E. Luce,J. Slattery +16 more
TL;DR: In this paper, the first fully integrated ULSI CMOS/copper interconnect technology is presented, where up to 6 Cu wiring levels are built at minimum metal-contacted pitch of 0.63 /spl mu/m, with W local-interconnect and contact levels and a poly-contacting pitch of 1.81 /spl µ/m.
Patent
Semiconductor device and manufacturing method thereof
Azuma Masahiko,Murai Hiroshi +1 more
TL;DR: In this article, the authors proposed to use a dummy gate and side wall spacer to keep the flexibility of mask material and arrangement of a gate electrode when a halo region is formed at a semiconductor device having a damascene gate structure.
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A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
Kaizad Mistry,C. Allen,C. Auth,B. Beattie,Daniel B. Bergstrom,M. Bost,M. Brazier,M. Buehler,Annalisa Cappellani,R. Chau,C. H. Choi,G. Ding,K. Fischer,Tahir Ghani,R. Grover,W. Han,D. Hanken,M. Hattendorf,J. He,J. Hicks,R. Huessner,D. Ingerly,Pulkit Jain,R. James,L. Jong,Subhash M. Joshi,C. Kenyon,K. Kuhn,K. Lee,Huichu Liu,J. Maiz,B. Mclntyre,P. Moon,J. Neirynck,S. Pae,C. Parker,D. Parsons,Chetan Prasad,L. Pipes,M. Prince,Pushkar Ranade,T. Reynolds,J. Sandford,Lucian Shifren,J. Sebastian,J. Seiple,D. Simon,Swaminathan Sivakumar,Pete Smith,C. Thomas,T. Troeger,P. Vandervoorn,S. Williams,K. Zawadzki +53 more