Proceedings ArticleDOI
Modified constant delay logic
K. Vishnuvardhan Rao,A. Anita Angeline,V. S. Kanchana Bhaaskaran +2 more
- pp 1093-1097
TLDR
A modified timing block is proposed which yields minimized area even while accomplishing the function, and across cascaded stages employing the proposed timing block realises a larger area reduction and hence reduction in power dissipation.Abstract:
The constant delay (CD) logic makes high speed operation of the dynamic circuits possible In the CD logic, the timing block plays a vital role as it helps in reduction of the evaluation time, by defining a small window width This paper proposes a modified timing block which yields minimized area even while accomplishing the function Use of the CD logic across cascaded stages employing the proposed timing block realises a larger area reduction and hence reduction in power dissipation All the simulations are done using UMC 90nm technology node library at 1GHz frequencyread more
References
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Book
Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.
Patent
Digital integrated circuits
TL;DR: Digital Integrated Circuits addresses today's most significant and compelling industry topics, including: the impact of interconnect, design for low power, issues in timing and clocking, design methodologies, and the tremendous effect of design automation on the digital design perspective.
Journal ArticleDOI
Analysis of High-Performance Fast Feedthrough Logic Families in CMOS
TL;DR: Experimental results demonstrate that low-power FTL provides for smaller propagation time delay, lower energy consumption, and similar combined delay, power consumption and active area product, while providing lower sensitivity to power supply, temperature, capacitive load and process variations than the standard CMOS technologies.
Journal ArticleDOI
Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance
Sohan Purohit,Martin Margala +1 more
TL;DR: This paper presents the design and characterization of 12 full-adder circuits in the IBM 90-nm process, including three new full-adders circuits using the recently proposed split-path data driven dynamic logic.
Journal ArticleDOI
Constant Delay Logic Style
TL;DR: A constant delay (CD) logic style is proposed in this paper, targeting at full-custom high-speed applications, and exhibits a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage is ready.