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Proceedings ArticleDOI

Multiple-detect ATPG based on physical neighborhoods

TLDR
A new ATPG strategy is presented that uses a new metric to capture quality of a multiple-detect test set based on the number of unique states on lines in the physical neighborhood of a targeted line to generate higher quality test sets.
Abstract
Multiple-detect test sets detect single stuck line faults multiple times, and thus have a higher probability of detecting complex defects. But current definitions of what constitutes a new test for a single stuck line fault do not leverage defect locality. Recent work has proposed a new metric to capture quality of a multiple-detect test set based on the number of unique states on lines in the physical neighborhood of a targeted line. This paper presents a new ATPG strategy that uses this metric to generate higher quality multiple-detect test sets.

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Citations
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Proceedings ArticleDOI

Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects

TL;DR: This paper shows that embedding multi-detection of faults within regular ATPG patterns results in a higher quality without a significant increase in test set size.
Proceedings ArticleDOI

Physically-aware N-detect test pattern selection

TL;DR: This work presents a test selection procedure for creating a physically- aware N-detect test set that satisfies a user-provided constraint on test-set size and shows that it can virtually detect the same number of faults 10 or more times as a traditional 10-detECT test set without increasing the number of tests.
Proceedings ArticleDOI

Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects

TL;DR: Investigation using test chips showed that the steady state voltage on open nets may drift slowly with the application of circuit inputs and can be different at different nets.
Patent

Method for testing integrated circuits

TL;DR: In this paper, the authors propose a method of testing an integrated circuit by selecting a set of physical features of nets and devices of the integrated circuit and assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment.
Proceedings ArticleDOI

Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study

TL;DR: A comprehensive comparative analysis about the effectiveness of deterministic bridge fault patterns and n-detect patterns for two large designs (90 and 65nm) shows that extracting different types of bridge faults is required as they represent different unique defect sites.
References
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Proceedings ArticleDOI

An experimental chip to evaluate test techniques experiment results

TL;DR: This paper describes the testing of a chip especially designed to facilitate the evaluation of various test techniques for combinational circuitry and the different test sets and test conditions are described.
Journal ArticleDOI

Yield estimation model for VLSI artwork evaluation

TL;DR: In this article, a model which describes limitations of a manufacturing yield in terms of an IC artwork and a lithography characterisation is proposed, where density and distribution of diameters of defects present in the mask, as well as line width fluctuations, are taken into account.
Proceedings ArticleDOI

Impact of multiple-detect test patterns on product quality

TL;DR: An ATPG tool is introduced that generates multiple-detect test patterns while maximizing the coverage of node-to-node bridging defects, and the experimental results from the project show that it demonstrates its robustness and adaptability.
Proceedings ArticleDOI

On n-detection test sets and variable n-detection test sets for transition faults

TL;DR: It is shown that the path delay fault coverage achieved by an n-detection transition fault test set increases significantly as n is increased, and a method is introduced to reduce the number of tests included in an n -detection test set by using different values of n for different faults based on their potential effect on the defect coverage.
Proceedings ArticleDOI

An experimental study of N-detect scan ATPG patterns on a processor

TL;DR: This paper studies the impact of N-detect scan ATPG patterns on test quality and associated test costs, and an incremental method for test generation is presented.
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