Proceedings ArticleDOI
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
Michael Huebner,Tobias Becker,Juergen Becker +2 more
- pp 28-32
Reads0
Chats0
TLDR
An overview of the used techniques and the complete system on a Xilinx XC2V3000 FPGA using slices instead of TBUF elements which leads to a benefit by using an automatic modular design flow.Abstract:
Xilinx Virtex FPGAs offer the possibility of dynamic and partial run-time reconfiguration. If a system uses this feature the designer has to take care, that no signal lines cross the border to other reconfigurable regions. Traditional solutions connecting modules on a dynamic and partial reconfigurable system use TBUF elements for connection and separation of the functional blocks. While automatically placing and routing the design, the routing-tool sometimes uses signal lines which cross the module border. The constraints given by the designer are ignored. To solve this problem, we use slices instead of TBUF elements which leads to a benefit by using an automatic modular design flow. This paper gives an overview of the used techniques and the complete system on a Xilinx XC2V3000 FPGA.read more
Citations
More filters
Proceedings ArticleDOI
Run-time Partial Reconfiguration speed investigation and architectural design space exploration
TL;DR: This paper proposes to use Direct Memory Access (DMA), Master (MST) burst, and a dedicated Block RAM (BRAM) cache respectively to reduce the reconfiguration time by one order of magnitude.
Journal ArticleDOI
Modular dynamic reconfiguration in Virtex FPGAs
TL;DR: In this paper, the authors compare and contrast two methods for implementing modular reconfiguration in Virtex FPGAs, one of which offers simplicity and fast reconfigure times, but limits the geometry and connectivity of the system.
Journal ArticleDOI
Dynamic and Partial FPGA Exploitation
TL;DR: A new adaptive software/hardware reconfigurable system is presented in this paper, using a real application in the automotive domain implemented on a Xilinx Virtex-II 3000 FPGA to present results.
Journal ArticleDOI
FPGA Dynamic and Partial Reconfiguration: A Survey of Architectures, Methods, and Applications
Kizheppatt Vipin,Suhaib A. Fahmy +1 more
TL;DR: This work reviews FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures, and investigates design flows and identifies the key challenges in making reconfigurable FPGAs systems easier to design.
Proceedings ArticleDOI
Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration
TL;DR: A method is introduced that circumvents the problem of having to find fully identical regions based on compatible subsets of resources, enabling flexible placement of relocatable modules on the FPGA.
References
More filters
Proceedings ArticleDOI
Networks on Chip: A New Paradigm for Systems on Chip Design
G. De Micheli,Luca Benini +1 more
TL;DR: The premises are that a component-based design methodology will prevail in the future, to support component re-use in a plug-and-play fashion, and SoCs will have to provide a functionally-correct, reliable operation of the interacting components.
Proceedings ArticleDOI
An FPGA run-time system for dynamical on-demand reconfiguration
TL;DR: This contribution presents a first approach for a flexible versatile FPGA-based run-time system supporting a resource saving function multiplex for a growing number of engine control units.
Proceedings ArticleDOI
A Lightweight Approach for Embedded Reconfiguration of FPGAs
TL;DR: A hardware and software infrastructure is reported that enables an FPGA to dynamically reconfigure itself under the control of a soft microprocessor core that is instantiated on the same array.
Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations
TL;DR: An important feature in the Xilinx VirtexTM architecture is the ability to reconfigure a portion of the FPGA while the remainder of the design is still operational.
Proceedings ArticleDOI
Power estimation and power measurement of Xilinx Virtex FPGAs: trade-offs and limitations
TL;DR: The exact power consumption trade-offs between the measured runtime consumption of a mapped application and the measured reconfiguration-time consumption of different dynamically (partially and completely) reconfigured applications are discussed.