Proceedings ArticleDOI
REPLICA: a bitstream manipulation filter for module relocation in partial reconfigurable systems
H. Kalte,G. Lee,Mario Porrmann,Ulrich Rückert +3 more
- pp 151
TLDR
The REPLICA (relocation per online configuration alteration) filter is developed, which is capable of performing the necessary bitstream manipulations during the regular download process and enables the integration of dynamic systems that can be adapted to changing demands during runtime.Abstract:
The feature of partial reconfiguration provided by currently available field programmable gate arrays (FPGAs) makes it possible to change hardware modules while others keep working. The combination of this feature and the high gate capacity enables the integration of dynamic systems that can be adapted to changing demands during runtime. Placing the dynamically changing modules along a horizontal communication infrastructure does not only provide communication facilities it also enables the relocation of pre-synthesized modules by bitstream manipulations. The exact placement of an incoming module is determined according to the current resource allocation, which results in an online placement problem. In order to prevent any extra configuration overhead for the relocation process, we developed the REPLICA (relocation per online configuration alteration) filter, which is capable of performing the necessary bitstream manipulations during the regular download process. The filter architecture, a configuration manager and an evaluation example are presented in this paper.read more
Citations
More filters
Proceedings ArticleDOI
Context saving and restoring for multitasking in reconfigurable systems
H. Kalte,Mario Porrmann +1 more
TL;DR: This paper discusses ways to save and restore the state information of a hardware task, and significantly reduces the amount of readback data by reading only those configuration frames that contain state information.
Journal ArticleDOI
FPGA Dynamic and Partial Reconfiguration: A Survey of Architectures, Methods, and Applications
Kizheppatt Vipin,Suhaib A. Fahmy +1 more
TL;DR: This work reviews FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures, and investigates design flows and identifies the key challenges in making reconfigurable FPGAs systems easier to design.
Proceedings ArticleDOI
Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration
TL;DR: A method is introduced that circumvents the problem of having to find fully identical regions based on compatible subsets of resources, enabling flexible placement of relocatable modules on the FPGA.
Proceedings ArticleDOI
REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs
H. Kalte,Mario Porrmann +1 more
TL;DR: The REPLICA2Pro (Relocation per online Configuration Alteration in Virtex-2/-Pro) filter is developed, which is capable of performing task relocations by manipulating the task's bitstream during the regular allocation process without any extra time overhead.
Journal ArticleDOI
Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration
TL;DR: This paper proposes a relocation filter that can be implemented both as a hardware and a software component, and can be customized to meet all the different constraints associated with these different target architectures.
References
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Proceedings ArticleDOI
A dynamic instruction set computer
Michael Wirthlin,Brad Hutchings +1 more
TL;DR: A dynamic instruction set computer (DISC) has been developed that supports demand-driven modification of its instruction set and enhances the functional density of FPGAs by physically relocating instruction modules to available FPGA space.
Proceedings ArticleDOI
Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation
Zhiyuan Li,Scott Hauck +1 more
TL;DR: This paper has developed prefetching algorithms that significantly reduce the reconfiguration overhead by overlapping the configuration loadings with the computation on the host processor.
Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations
TL;DR: An important feature in the Xilinx VirtexTM architecture is the ability to reconfigure a portion of the FPGA while the remainder of the design is still operational.
Proceedings ArticleDOI
Configuration compression for the Xilinx XC6200 FPGA
TL;DR: An algorithm is developed, targeted to the decompression hardware imbedded in the Xilinx XC6200 series FPGA architecture, that can radically reduce the amount of data needed to transfer during reconfiguration, resulting in an overall reduction of almost 4 in total bandwidth required for reconfigurations.
PARBIT: A Tool to Transform Bitfiles to Implement Partial Reconfiguration of Field Programmable Gate Arrays (FPGAs)
TL;DR: A tool called PARBIT has been developed that transforms FPGA configuration bitfiles to enable DHP modules and it is possible to define a partial reconfigurable area inside the FPGAs and download it into a specified region of the FGPA device.