Journal ArticleDOI
New and improved architectures for Montgomery modular multiplication
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An improved Montgomery multiplier, based on modified four-to-two carry-save adders (CSAs) to reduce critical path delay, is presented and a new bit-sliced, unified and scalable Montgomery multiplier architecture, applicable for both RSA and ECC, is proposed.Abstract:
In this paper an improved Montgomery multiplier, based on modified four-to-two carry-save adders (CSAs) to reduce critical path delay, is presented Instead of implementing four-to-two CSA using two levels of carry-save logic, authors propose a modified four-to-two CSA using only one level of carry-save logic taking advantage of pre-computed input values Also, a new bit-sliced, unified and scalable Montgomery multiplier architecture, applicable for both RSA and ECC (Elliptic Curve Cryptography), is proposed In the existing word-based scalable multiplier architectures, some processing elements (PEs) do not perform useful computation during the last pipeline cycle when the precision is not equal to an exact multiple of the word size, like in ECC This intrinsic limitation requires a few extra clock cycles to operate on operand lengths which are not powers of 2 The proposed architecture eliminates the need for extra clock cycles by reconfiguring the design at bit-level and hence can operate on any operand length, limited only by memory and control constraints It requires 2∼15% fewer clock cycles than the existing architectures for key lengths of interest in RSA and 11∼18% for binary fields and 10∼14% for prime fields in case of ECC An FPGA implementation of the proposed architecture shows that it can perform 1,024-bit modular exponentiation in about 15 ms which is better than that by the existing multiplier architecturesread more
Citations
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Journal ArticleDOI
Bit-serial and digit-serial GF(2 m )Montgomery multipliers using linear feedback shift registers
TL;DR: The results show that the use of LFSRs simplifies the design of the multipliers architecture reducing area resources and retaining high performance compared to related works.
Journal ArticleDOI
Area/performance trade-off analysis of an FPGA digit-serial GF(2m) Montgomery multiplier based on LFSR
TL;DR: Alternative architectures for constructing GF(2^m) digit-serial Montgomery multipliers on FPGAs based on Linear Feedback Shift Registers (LFSRs) are explored and their area-performance trade-offs are studied to show a notable improvement against FPGA Montgomery multiplier.
Proceedings ArticleDOI
An Implementation of Montgomery Modular Multiplication on FPGAs
TL;DR: The experimental results show that the throughput of 856.9 million modular multiplications per second can be achieved and the hybrid Montgomery modular multiplier has an outstanding performance in the situations which need continuous multiplications.
Journal ArticleDOI
High-performance scalable architecture for modular multiplication using a new digit-serial computation
TL;DR: A new scalable Montgomery modular multiplication architecture with variable-radix design with one clock cycle delay in data flow is proposed, which has area×time complexity and performance advantages compared to related algorithms/architectures.
Journal ArticleDOI
Design of RSA processor for concurrent cryptographic transformations
TL;DR: A Bit Forwarding 1-bit (BFW1) algorithm has been implemented to evaluate modular exponentiation that resulted in 11.11% improvement in throughput, and 1.90% reduction in power consumption.
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