On-chip automatic tuning for a CMOS continuous-time filter

TLDR: In this article, the authors present a complete, integrated system including a fifth-order elliptic low-pass filter and a Phase-Locked Loop (PLL) control circuit for the automatic tuning of the filter.

Abstract: A TECHNIQUE BASED ON FULLY-BALANCED topologies was recently introduced for the design of monolithic active RC filters in MOS technology’. These circuits work in continuoustime, have a wide dynamic range and are voltage tunable. The latter capability can be used to reference accurately their frequency responses to an external clock signal similar to another method2. This report will present a complete, integrated system including a fifth-order elliptic low-pass filter and a Phase-Locked Loop (PLL) control circuit for the automatic tuning of the filter. The system diagram is shown in Figure 1, and the chip microphotograph in Figure 2. The fabrication technology was a twintub CMOS with 3.5p minimum linewidths. The power supplies used were I5V. The design followed closely the classical method of active RC circuits. The filter was synthesized from a passive RLC ladder network using a ladder-simulation technique. The element values were chosen so that a standard elliptic transfer could be realized. The transistors used as voltage-controlled resistors with nonlinearity cancelation’ and the capacitors were scaled properly pair by pair to optimize the filter for dynamic range;in such balanced networks all capacitors and MOSFET resistors appear in pairs of identical elements. A 0.5dB peaking in the frequency response due to opamp finite bandwidth and transistor intrinsic distributed parasitic capacitances was eliminated at the simulation stage by slightly modifying the values of two capacitors in a pair. The channel width of the transistors was 4 p and the channel lengths were 1 6 0 ~ 200p and 400p (channel length of unit transistor was 40p; no cross-connecting was used for easy layout). The balanced operational amplifiers were implemented with pairs of regular operational amplifiers and p t u b resistors for simplicity. Their unity-gain bandwidth is 1MHz. The voltage-controlled oscillator (VCO) of the PLL was implemented with a second-order fully-balanced active RC network. Ideally, this state-variable topology realizes poles precisely on the jw axis. Since the predictable nonidealities of this circuit automatically ensures it instability, no special care had to be taken to produce oscillations. To limit the output signal level, thus preserving good spectral purity, two diodeconnected transistors were added. The transistors and capacitors of the VCO were laid out in close proximity to the respective elements of the filter as shown in Figure 2. This is important to improve the frequency characteristics matching of the master VCO with the s h e filter. Two voltage-comparators were used to guarantee that the inputs to the phase comparator are square -