Proceedings ArticleDOI
On generating high quality tests based on cell functions
Xijiang Lin,Sudhakar M. Reddy +1 more
- pp 1-9
TLDR
A single set of tests based on functional description of CMOS cells that are more complex than primitive gates are derived, if applied, to detect multiple stuck-at faults, multiple transistor stuck-open faults, cross wire open faults, delay faults and bridging faults between inputs of the cell.Abstract:
In this paper we consider detection of faults in CMOS cells that are more complex than primitive gates. We derive a single set of tests based on functional description of the cells. The tests derived, if applied, detect multiple stuck-at faults, multiple transistor stuck-open faults, cross wire open faults, delay faults and bridging faults between inputs of the cell, in any implementation of the cell functions. We give results on an industrial design to demonstrate the benefits of the proposed tests relative to standard stuck-at, cell exhaustive and transition fault tests in covering faults in such cells.read more
Citations
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Proceedings ArticleDOI
DFM-aware fault model and ATPG for intra-cell and inter-cell defects
TL;DR: A novel automated flow for cell characterization that can be used to create patterns at the cell boundary for DFM-aware faults is described, which compares with the cell-aware and dual-cell-aware fault models, and describes relative advantages and application scenarios.
Proceedings ArticleDOI
Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation
TL;DR: This paper proposes methods to drastically reduce the expensive analog fault simulation currently used to create cell-aware fault models by exploiting low-power properties of common CMOS designs, and shows that faulty behaviors are completely predictable as the defect resistance parameter value varies from zero to infinity, thus eliminating the need for circuit simulation at multiple parameter values.
Proceedings ArticleDOI
Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology
TL;DR: This work identifies defects of certain sizes that can go undetected by current methods and proposes an algorithmic approach towards cell characterization that can result in faster identification of cell input stimuli vis-a-vis a defect simulation based method.
Proceedings ArticleDOI
Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG
TL;DR: A waveform-accurate hazard-aware test generation approach to target intra-gate opens based on a SAT-based encoding that allows the generation of tests guaranteed to be robust against hazards and can be applied to improve the effectiveness of commercial cell aware tests.
Proceedings ArticleDOI
Transistor stuck-on fault detection tests for digital CMOS circuits
TL;DR: This work proposes generation of logic tests based on Boolean functions implemented by the gates in CMOS digital logic circuits, and shows that, when available, the tests proposed should be preferred over earlier proposed IDDQ based tests.
References
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Book
Digital Systems Testing and Testable Design
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Proceedings Article
Model for Delay Faults Based Upon Paths
TL;DR: A procedure is described which identifies paths which are tested for path faults by a set of patterns, independent of the delays of any individual gate of the network, which is a global delay fault model.
Journal ArticleDOI
Transition Fault Simulation
TL;DR: The authors present a model, called a transition fault, which when used with parallel-pattern, single-fault propagation, is an efficient way to simulate delay faults and shows that delay fault simulation can be done of random patterns in less than 10% more time than needed for a stuck fault simulation.
Journal ArticleDOI
Bridging and Stuck-At Faults
TL;DR: The commonly used stuck-at fault fails to model logic circuit shorts, so Bridging faults are defined to model these circuit mal-functions.
Proceedings ArticleDOI
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
F.J. Ferguson,T. Larrabee +1 more
TL;DR: This paper simulates complete single stuck-at test sets against a low-level model of bridge defects showing that an unacceptably high percentage of such defects are not detected by the complete stuck- at test sets.