On maximum contention-free interleavers and permutation polynomials over integer rings
TLDR
It is shown that permutation polynomials generate maximum contention-free interleavers, i.e., every factor of the interleaver length becomes a possible degree of parallel processing of the decoder.Abstract:
An interleaver is a critical component for the channel coding performance of turbo codes. Algebraic constructions are of particular interest because they admit analytical designs and simple, practical hardware implementation. Contention-free interleavers have been recently shown to be suitable for parallel decoding of turbo codes. In this correspondence, it is shown that permutation polynomials generate maximum contention-free interleavers, i.e., every factor of the interleaver length becomes a possible degree of parallel processing of the decoder. Further, it is shown by computer simulations that turbo codes using these interleavers perform very well for the Third Generation Partnership Project (3GPP) standardread more
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Patent
Method and apparatus for encoding and decoding data
TL;DR: In this article, a structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix Hb and wherein Hb comprises a section Hb1 and a section hb2, and Hb2 comprises a first part comprising a column hb having an odd weight greater than 2, and a second part comprising matrix elements for row i, column j equal to 1 for i=j, 1 for j+1, and 0 elsewhere.
Journal ArticleDOI
Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE
TL;DR: The design and implementation aspects of parallel turbo-decoders that reach the 326.4 Mb/s LTE peak data-rate using multiple soft-input soft-output decoder that operate in parallel are addressed.
Journal ArticleDOI
Soft-decision decoding of Reed-Muller codes: recursive lists
Ilya Dumer,Kirill Shabunov +1 more
TL;DR: Simulation results show that for all RM codes of length 256 and many subcodes of length 512, these algorithms approach maximum-likelihood (ML) performance within a margin of 0.1 dB.
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Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder
Yang Sun,Joseph R. Cavallaro +1 more
TL;DR: A low-complexity QPP interleaving address generator and a multi-bank memory architecture to enable parallel Turbo decoding and design trade-offs in terms of area and throughput efficiency are explored to find the optimal architecture.
Proceedings ArticleDOI
On 3G LTE Terminal Implementation - Standard, Algorithms, Complexities and Challenges
TL;DR: It is shown that the inner receiver can nicely and straightforwardly be parallelized due to frequency domain processing, and one of the challenges is an efficient implementation considering necessary flexibility for different MIMO modes, power consumption and silicon area.
References
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Book
An Introduction to the Theory of Numbers
TL;DR: The fifth edition of the introduction to the theory of numbers has been published by as discussed by the authors, and the main changes are in the notes at the end of each chapter, where the author seeks to provide up-to-date references for the reader who wishes to pursue a particular topic further and to present a reasonably accurate account of the present state of knowledge.
Proceedings ArticleDOI
Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1
TL;DR: In this article, a new class of convolutional codes called turbo-codes, whose performances in terms of bit error rate (BER) are close to the Shannon limit, is discussed.
Weight distributions for turbo codes using random and nonrandom permutations
TL;DR: From probabilistic arguments based on selecting the permutations randomly, it is concluded that the self-terminating weight-2 data sequences are the most important consideration in the design of the constituent codes; higher-weight self- terminating sequences have successively decreasing importance.