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Journal ArticleDOI

Parallel architectures for 3-step hierarchical search block-matching algorithm

TLDR
The paper describes fully pipelined parallel architectures for the 3-step hierarchical search block-matching algorithm, a fast motion estimation algorithm for video coding, which provide efficient solutions for real-time motion estimations required by video applications of various data rates, from low bit-rate video to HDTV systems.
Abstract
The paper describes fully pipelined parallel architectures for the 3-step hierarchical search block-matching algorithm, a fast motion estimation algorithm for video coding. The advantage of this algorithm was completely utilized by use of intelligent data arrangement and memory configuration. Techniques for reducing interconnections and external memory accesses were also developed. Because of their low costs, high speeds, and low memory bandwidth requirements, the proposed 3-PE, 9-PE, and 27-PE architectures provide efficient solutions for real-time motion estimations required by video applications of various data rates, from low bit-rate video to HDTV systems. >

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Citations
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Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation

TL;DR: Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation is an important introduction to numerous algorithmic, architectural and system design aspects of the multimedia standard MPEG-2 and H.263.
Journal ArticleDOI

A simple and efficient search algorithm for block-matching motion estimation

TL;DR: It is shown that the proposed algorithm is simple and efficient and requires about one half of the computation for the TSS while keeping the same regularity and good performance.
Journal ArticleDOI

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

TL;DR: Two hardware architectures are proposed that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches and an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation is proposed.
Journal ArticleDOI

Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results

TL;DR: The main idea is quick checking of the entire search range with simplified matching criterion to globally eliminate impossible candidates, followed by finer selection among potential best matched candidates.
Journal ArticleDOI

Low-power VLSI design for motion estimation using adaptive pixel truncation

TL;DR: A novel method of reducing power consumption of the ME by adaptively changing the pixel resolution during the computation of the motion vector is proposed, which results in more than 60% reduction in power consumption.
References
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Journal ArticleDOI

Displacement Measurement and Its Application in Interframe Image Coding

TL;DR: The motion compensation is applied for analysis and design of a hybrid coding scheme and the results show a factor of two gain at low bit rates.
Journal ArticleDOI

Predictive Coding Based on Efficient Motion Estimation

TL;DR: A computationally simpler and effective method is proposed for estimating motion in a video sequence based on conjugate directions and another simpler technique called the one-at-a-time search, adopted as the basis for further research.
Journal ArticleDOI

The cross-search algorithm for motion estimation (image coding)

TL;DR: Using sequences of CIF standard pictures, the interframe motion compensated prediction error with this technique is compared to the other fast methods and the computational complexity of this algorithm is compared against those methods.
Journal ArticleDOI

A family of VLSI designs for the motion compensation block-matching algorithm

TL;DR: In this article, a family of modular VLSI architectures and chip implementations of the motion-compensation full-search block-matching algorithm are described, motivated by the intensive computations required to perform motion compensation in real time.
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