Journal ArticleDOI
Power-effective ROM-less DDFS Design Approach with High SFDR Performance
Reads0
Chats0
TLDR
A ROM-less direct digital frequency synthesizer (DDFS) design approach based on interpolation schemes that achieves higher SFDR and faster clock rate and is proved to outperform many previous DDFS works even if they were implemented on silicon.Abstract:
A ROM-less direct digital frequency synthesizer (DDFS) design approach based on interpolation schemes is proposed in this work. Besides achieving higher SFDR (spurious free dynamic range) and faster clock rate, detailed power estimation approach based on switching activity analysis of each logic sub-blocks is presented to explore the optimal solution. The parabolic equations with proper selection of coefficients and pipeline structure are utilized to enhance SFDR. A ROM-less DDFS using the proposed design approach is demonstrated by the physical implementation on Altera FPGA platform. The average SFDR is measured to be 68.4242 dBc with 1.1659 dBc deviation over 33 times of experiments. The measured SFDR is proved to outperform many previous DDFS works even if they were implemented on silicon.read more
Citations
More filters
Journal ArticleDOI
Low-Power Low-Cost Direct Digital Frequency Synthesizer Using 90 nm CMOS Technology
TL;DR: The proposed logarithm-based DDFS scheme demonstrates a reduction in power dissipation with respect to previously proposed work and produces a spurious-free dynamic range (SFDR) of up to 117 dBc.
Proceedings ArticleDOI
Design of three-phase SPWM inverter controller based on FPGA
Lina Sun,Hao Lu,Jianshen Li +2 more
TL;DR: In this article , a realization scheme of SPWM (Sinusoidal Pulse Width Modulation) controller based on Field Programmable Gate Array (FPGA) is proposed, which is mainly composed of a waveform generator and a SPWM generator.
References
More filters
Journal ArticleDOI
A digital frequency synthesizer
TL;DR: The digital technique lends itself to the production of phase coherent or phase controlled sinusoids because of the indexing arrangement used and finer frequency steps than the READ-ONLY memory allows are available by expanding theindexing register at no increase in inaccuracy.
Journal ArticleDOI
An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC
TL;DR: This paper presents a low power, ultrahigh-speed and high resolution SiGe DDS MMIC with 11-bit phase and 10-bit amplitude resolutions, as well as a leading power efficiency figure-of-merit (FOM) of 81.1 GHz·2SFDR/6/W in the mm-wave DDS design.
Journal ArticleDOI
Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency
TL;DR: A high-speed phase-adjustable read-only-memory less direct digital frequency synthesizer employing trigonometric quadruple angle formula is presented, which is far higher than the 32-MHz requirement of Korean personal communications system, global system for mobile communications, and Bluetooth.
Journal ArticleDOI
Low-Noise Microwave Performance of 0.1 $\mu$ m Gate AlInN/GaN HEMTs on SiC
Haifeng Sun,A.R. Alt,H. Benedickter,Eric Feltin,Jean-François Carlin,M Gonschorek,Nicolas Grandjean,Colombo R. Bolognesi +7 more
TL;DR: In this article, the first microwave noise characterization of AlInN/GaN HEMTs was reported, with a 0.1 μ m gate implemented on a semi-insulating SiC substrate achieving a maximum current density of 1.92 A/mm at VGS = 0 V, measured transconductance gM = 480 mS/mm, and peak current gain cutoff frequency fT = 121 GHz with a simultaneous maximum oscillation frequency fMAX = 142 GHz.
Journal ArticleDOI
A Fast Settling Dual-Path Fractional- $N$ PLL With Hybrid-Mode Dynamic Bandwidth Control
TL;DR: In this paper, the authors employed a dynamic gain-bandwidth control scheme for both coarse-tuning and fine-tuned paths with compensated open-loop gain design, which results in a smooth transition from transient to normal mode.