Journal ArticleDOI
Reconfigurable Hardware Architecture for Authenticated Key Agreement Protocol Over Binary Edwards Curve
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The implementation results show that the proposed architecture is resistant against SPA attack and yields a better performance when compared to the existing state-of-the-art BEC designs for computing point multiplication (PM).Abstract:
In this article, we present a high-performance hardware architecture for Elliptic curve based (authenticated) key agreement protocol “Elliptic Curve Menezes, Qu and Vanstone” (ECMQV) over Binary Edwards Curve (BEC). We begin by analyzing inversion module on a 251-bit binary field. Subsequently, we present Field Programmable Gate Array (FPGA) implementations of the unified formula for computing elliptic curve point addition on BEC in affine and projective coordinates and investigate the relative performance of these two coordinates. Then, we implement the w-coordinate based differential addition formulae suitable for usage in Montgomery ladder. Next, we present a novel hardware architecture of BEC point multiplication using mixed w-coordinates of the Montgomery laddering algorithm and analyze it in terms of resistance to Simple Power Analysis (SPA) attack. In order to improve the performance, the architecture utilizes registers efficiently and uses efficient scheduling mechanisms for the BEC arithmetic implementations. Our implementation results show that the proposed architecture is resistant against SPA attack and yields a better performance when compared to the existing state-of-the-art BEC designs for computing point multiplication (PM). Finally, we present an FPGA design of ECMQV key agreement protocol using BEC defined over GF(2251). The execution of ECMQV protocol takes 66.47μs using 32,479 slices on Virtex-4 FPGA and 52.34μs using 15,988 slices on Virtex-5 FPGA. To the best of our knowledge, this is the first FPGA design of the ECMQV protocol using BEC.read more
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Journal ArticleDOI
FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures
TL;DR: An extensive survey on the current state-of-the-art of FPGA based Physically Unclonable Functions, and a detailed performance evaluation result for several FGPA based PUF designs and their comparisons are provided.
Journal ArticleDOI
Efficient and Lightweight FPGA-based Hybrid PUFs with Improved Performance
TL;DR: This paper presents an area efficient hybrid PUF design on field-programmable gate array (FPGA) that combines units of conventional RS Latch-based PUF and Arbiter- based PUF which is then augmented by the programmable delay lines (PDLs) and Temporal Majority Voting (TMV) for performance enhancement.
Journal ArticleDOI
A 4-Stage Pipelined Architecture for Point Multiplication of Binary Huff Curves
TL;DR: This work has proposed a 4-stage pipelined architecture to achieve an optimized throughput over area ratio for point multiplication (PM) computation in binary huff curves (BHC) cryptography.
Journal ArticleDOI
Field Programmable Gate Array based elliptic curve Menezes-Qu-Vanstone key agreement protocol realization using Physical Unclonable Function and true random number generator primitives
TL;DR: In this article , an efficient Field Programmable Gate Array (FPGA)-based implementation of elliptic curve Menezes-Qu-Vanstone (ECMQV)-authenticated key agreement protocol using PUF and TRNG with very competitive area-throughput trade-offs is presented.
Journal Article
PQC-SEP: Power Side-channel Evaluation Platform for Post-Quantum Cryptography Algorithms
Jung-Gik Park,N. Nalla Anandakumar,Dipayan Saha,Dhwani Mehta,Nitin Pundir,Fahim Rahman,Farimah Farahmandi,Mark Tehranipoor +7 more
TL;DR: PQC-SEP is evaluated, a completely automated side-channel evaluation platform at both pre- and post-silicon levels, that automatically estimates the amount of side- channel leakage in the power of a PQC design at early design stages and validates side-Channel leakages at the post- silicon level against artificial intelligence (AI) based SCA models and traditional SCA model.
References
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