scispace - formally typeset
Open AccessJournal ArticleDOI

FPGA Dynamic and Partial Reconfiguration: A Survey of Architectures, Methods, and Applications

Reads0
Chats0
TLDR
This work reviews FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures, and investigates design flows and identifies the key challenges in making reconfigurable FPGAs systems easier to design.
Abstract
Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs). While they have been studied extensively in academic literature, they find limited use in deployed systems. We review FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures. We then investigate design flows and identify the key challenges in making reconfigurable FPGA systems easier to design. Finally, we look at applications where reconfiguration has found use, as well as proposing new areas where this capability places FPGAs in a unique position for adoption.

read more

Content maybe subject to copyright    Report

Citations
More filters
Proceedings Article

DPGA Utilization and Application

TL;DR: In this paper, the authors examine several usage patterns for DPGAs including temporal pipelining, utility functions, multiple function accommodation, and state-dependent logic, and offer insight into the application and technology space where DPGA-style reuse techniques are most beneficial.
Posted Content

A Survey of FPGA-Based Robotic Computing

TL;DR: An overview of previous work on FPGA-based robotic accelerators covering different stages of the robotic system pipeline is given and an analysis of software and hardware optimization techniques and main technical issues is presented to serve as a guide for future work.
Journal ArticleDOI

PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration

TL;DR: The proposed scheme is based on the use of lookup tables (LUTs) and partial reconfiguration to achieve a more effective use of the FPGA resources while supporting the addition and removal of rules.
Proceedings ArticleDOI

PURR: a primitive for reconfigurable fast reroute: hope for the best and program for the worst

TL;DR: An FRR primitive for programmable data planes, PURR, which provides low failover latency and high switch throughput, by avoiding packet recirculation, and is well-suited for high-speed match-action forwarding architectures.
Proceedings ArticleDOI

Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration

TL;DR: A flexible accelerator called Transmuter is presented, in a novel effort to bridge the gap between General-Purpose Processors (GPPs) and Application-Specific Integrated Circuits (ASICs), which addresses a rapidly growing set of algorithms exhibiting dynamic data movement patterns, irregularity, and sparsity, while delivering GPU-like efficiencies for traditional dense applications.
References
More filters
Journal ArticleDOI

Reconfigurable computing: a survey of systems and software

TL;DR: The hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling are explored, and the software that targets these machines is focused on.
Proceedings ArticleDOI

Garp: a MIPS processor with a reconfigurable coprocessor

TL;DR: Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.
Proceedings ArticleDOI

A time-multiplexed FPGA

TL;DR: The architecture of a time-multiplexed FPGA is described, which includes extensions for dealing with state saving and forwarding and for increased routing demand due to time- multiplexing the hardware.
Journal ArticleDOI

Reconfigurable computing: architectures and design methods

TL;DR: It is shown that reconfigurable computing designs are capable of achieving up to 500 times speedup and 70% energy savings over microprocessor implementations for specific applications.
Related Papers (5)