Journal ArticleDOI
Resonant-tunneling mixed-signal circuit technology
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TLDR
In this article, a large-scale integration (LSI) InP-based technology is described for high-speed mixed-signal circuits, which uses molecular beam epitaxy, InP etch stop layers, an electron-beam defined gate, non-alloyed ohmic contacts, and 10 mask levels to provide resonant tunneling diodes.Abstract:
A large-scale integration (LSI) InP-based technology is described for high-speed mixed-signal circuits. The monolithic 75-mm wafer process uses molecular beam epitaxy, InP etch stop layers, an electron-beam-defined gate, non-alloyed ohmic contacts, and 10 mask levels to provide resonant tunneling diodes (RTD's), 0.25- or 0.5-μm gate-length high electron mobility transistors (HEMT's), Schottky diodes, resistors, capacitors and two and a half levels of interconnect. Resonant tunneling circuits described here for the first time include a 2.5-GHz, ten stage, tapped shift register, a 6.5-GHz clock generator and a multivalued-to-binary converter.read more
Citations
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Journal ArticleDOI
Tunneling-based SRAM
TL;DR: In this paper, a high-density low-power circuit approach for implementing static random access memory (SRAM) using low current density resonant tunneling diodes (RTDs) is described.
Patent
Charge trapping device and method for implementing a transistor having a negative differential resistance mode
Tsu-Jae King,David K. Y. Liu +1 more
TL;DR: In this article, a charge trapping structure for use with an n-channel metal-insulator-semiconductor field effect transistor (MISFET) is disclosed, where a dielectric layer is formed close to a channel region of the MISFET, and includes a number of trapping sites which are arranged and have a concentration sufficient to temporarily store energetic electrons induced by an electric field to move from the channel into the trapping sites.
Patent
A CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same
Tsu-Jae King,David K. Y. Liu +1 more
TL;DR: An n-channel metal-insulator-semiconductor field effect transistor (MISFET) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain voltage) is disclosed in this article.
Patent
Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET
TL;DR: In this paper, a semiconductor device is disclosed that includes integrated insulated-gate field-effect transistor (IGFET) elements and one or more negative differential resistance (NDR) field effect transistor elements, combined and formed on a common substrate.
Patent
Negative differential resistance field effect transistor (ndr-fet) & circuits using the same
TL;DR: In this paper, an improved negative differential resistance field effect transistor (NDR-FET) is proposed. But the NDR-fET is not suitable for memory cells, since it requires a single channel technology (i.e., instead of CMOS) and yet provides low power.
References
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Journal ArticleDOI
A monolithic 4-bit 2-Gsps resonant tunneling analog-to-digital converter
T.P.E. Broekaert,Bobby Brar,J.P.A. van der Wagt,Alan Seabaugh,Francis J. Morris,Theodore S. Moise,E.A. Beam,Gary A. Frazier +7 more
TL;DR: The first monolithic flash analog-to-digital converter (ADC) in this technology is demonstrated and characterized and the one-bit quantizer achieved a single-tone spurious free dynamic range greater than 40 dB at 2 Gsps for a 220-MHz single- Tone input with dithering.
Journal ArticleDOI
RTD/HFET low standby power SRAM gain cell
TL;DR: In this paper, a 50 nW standby power compound semiconductor tunneling-based static random access memory SRAM (TSRAM) cell is demonstrated by combining ultralow current-density resonant-tunneling diodes (RTDs) and heterostructure field effect transistors (HFETs) in one integrated process on an InP substrate.
Journal ArticleDOI
High-speed and low-power operation of a resonant tunneling logic gate MOBILE
TL;DR: In this article, high-speed operations up to 35 Gb/s were demonstrated for a resonant tunneling (RT) logic gate monostable-bistable transition logic element (MOBILE).
Journal ArticleDOI
Multiple-valued logic
TL;DR: Two prototype four-valued logic devices have been implemented at the University of Twente (Enschede, Holland) and Hitachi has implemented a 16-valued memory that stores the equivalent of 10/sup 6/ bits.