Patent
Semiconductor memory device with floating storage bulk region and method of manufacturing the same
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TLDR
In this article, a memory cell MC comprises one MOS transistor having a floating bulk region which is electrically isolated from others, and the memory cell stores a first threshold state in which majority carriers produced by impact ionization are injected and held in the bulk region 12 of the MOS transistors and a second threshold state, in which the majority carriers are emitted by a forward bias at a pn junction on the drain side as binary data.Abstract:
A memory cell MC comprises one MOS transistor having a floating bulk region which is electrically isolated from others. A gate electrode 13 of the MOS transistor is connected to a word line WL, a drain diffusion region 14 thereof is connected to a bit line BL, and a source diffusion region 15 thereof is connected to a fixed potential line SL. The memory cell stores a first threshold state in which majority carriers produced by impact ionization are injected and held in the bulk region 12 of the MOS transistor and a second threshold state in which the majority carriers in the bulk region 12 of the MOS transistor are emitted by a forward bias at a pn junction on the drain side as binary data. Thereby, a semiconductor memory device in which a simple transistor structure is used as a memory cell, enabling dynamic storage of binary data by a small number of signal lines can be provided.read more
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Semiconductor memory device and method of manufacturing the same
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References
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Patent
A capacitorless dram device on silicon-on-insulator substrate
Chenming Hu,Hsing-Jen Wann +1 more
TL;DR: In this paper, a DRAM device has a first semiconductor region (18) of one conductivity on the silicon film of a silicon-on-insulator substrate (22).
Journal ArticleDOI
The multistable charge-controlled memory effect in SOI MOS transistors at low temperatures
TL;DR: In this paper, a multistable charge-controlled memory (MCCM) effect is observed in SOI MOS transistors working at lot temperatures, which results in a controllable setting of the transistor threshold voltage by applying adequate voltage pulses (or updown voltage sweeps) to one or more electrodes of the structure.
Patent
Two-device memory cell on SOI for merged logic and memory applications
TL;DR: A two-MOSFET device memory cell, based on conventional SOI complementary metal oxide technology, was proposed in this article, in which charge is stored on the body of a first MOSFCET, with a second MOSFFCET connected to the body for controlling the charge in accordance with an information bit.
Patent
Methods to enhance SOI SRAM cell stability
TL;DR: In this paper, the authors proposed a level shifting of the "off" voltage applied to the gate electrode of the transfer gate transistor dynamically changes the gain of the cell transfer gate to increase memory cell stability without compromising the memory capacity per chip or read/write memory cycle time.
Patent
Semiconductor storage device
TL;DR: In this article, a memory cell transistor with a floating gage FG, a control gate CG and a source and a drain is provided, and voltage is lowered on write, and the erroneous erasing of a non selective cell is prevented while the generation of hot carriers at the time of read is inhibited and a software error can be obviated.