Signal Delay in RC Tree Networks
Paul Penfield,Jorge Rubinstein +1 more
- pp 421-425
TLDR
Upper and lower bounds for delay that are computationally simple are presented here to certify that a circuit is "fast enough", given both the maximum delay and the voltage threshold.Abstract:
In MOS integrated circuits, signals may propagate between stages with fanout. The MOS interconnect may be modeled by an RC tree. Exact calculation of signal delay through such networks is difficult. However, upper and lower bounds for delay that are computationally simple are presented here. The results can be used (1) to bound the delay, given the signal threshold; or (2) to bound the signal voltage, given a delay time; or (3) to certify that a circuit is "fast enough", given both the maximum delay and the voltage threshold.read more
Citations
More filters
Journal ArticleDOI
Asymptotic waveform evaluation for timing analysis
L.T. Pillage,R.A. Rohrer +1 more
TL;DR: Asymptotic waveform evaluation (AWE) provides a generalized approach to linear RLC circuit response approximations and reduces to the RC tree methods.
Journal ArticleDOI
A tutorial on geometric programming
TL;DR: This tutorial paper collects together in one place the basic background material needed to do GP modeling, and shows how to recognize functions and problems compatible with GP, and how to approximate functions or data in a formcompatible with GP.
Journal ArticleDOI
Signal Delay in RC Tree Networks
TL;DR: Upper and lower bounds for delay that are computationally simple are presented in this paper and can be used to bound the delay, given the signal threshold, and to certify that a circuit is "fast enough," given both the maximum delay and the voltage threshold.
Journal ArticleDOI
CACTI: an enhanced cache access and cycle time model
TL;DR: In this paper, an analytical model for the access and cycle times of on-chip direct-mapped and set-associative caches is presented, where the inputs to the model are the cache size, block size, and associativity, as well as array organization and process parameters.
Proceedings ArticleDOI
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
TL;DR: This paper proposes physical designs for these Non-Uniform Cache Architectures (NUCAs) and extends these physical designs with logical policies that allow important data to migrate toward the processor within the same level of the cache.
References
More filters
Journal ArticleDOI
The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers
TL;DR: It is found possible to define delay time and rise time in such a way that these quantities can be computed very simply from the Laplace system function of the network.
Journal ArticleDOI
Signal Delay in RC Tree Networks
TL;DR: Upper and lower bounds for delay that are computationally simple are presented in this paper and can be used to bound the delay, given the signal threshold, and to certify that a circuit is "fast enough," given both the maximum delay and the voltage threshold.
Proceedings ArticleDOI
The Analog Behavior of Digital Integrated Circuits
TL;DR: The problem of estimating signal propagation delays in VLSI circuits may be reduced to the problem of summing the step responses of a set of linear RC networks, which begins the formalization of the fundamental properties of digital integrated circuits.