Proceedings ArticleDOI
Simplify to survive: prescriptive layouts ensure profitable scaling to 32nm and beyond
Lars W. Liebmann,Larry Pileggi,Jason D. Hibbeler,Vyacheslav Rovner,Tejas Jhaveri,Greg Northrop +5 more
Reads0
Chats0
TLDR
The time-to-market driven need to maintain concurrent process-design co-development, even in spite of discontinuous patterning, process, and device innovation, is reiterated and shortcomings in traditional Design for Manufacturability solutions are identified.Abstract:
The time-to-market driven need to maintain concurrent process-design co-development, even in spite of discontinuous
patterning, process, and device innovation is reiterated. The escalating design rule complexity resulting from increasing
layout sensitivities in physical and electrical yield and the resulting risk to profitable technology scaling is reviewed.
Shortcomings in traditional Design for Manufacturability (DfM) solutions are identified and contrasted to the highly
successful integrated design-technology co-optimization used for SRAM and other memory arrays. The feasibility of
extending memory-style design-technology co-optimization, based on a highly simplified layout environment, to logic
chips is demonstrated. Layout density benefits, modeled patterning and electrical yield improvements, as well as
substantially improved layout simplicity are quantified in a conventional versus template-based design comparison on a
65nm IBM PowerPC 405 microprocessor core. The adaptability of this highly regularized template-based design
solution to different yield concerns and design styles is shown in the extension of this work to 32nm with an increased
focus on interconnect redundancy. In closing, the work not covered in this paper, focused on the process side of the
integrated process-design co-optimization, is introduced.read more
Citations
More filters
Journal ArticleDOI
Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings
Tejas Jhaveri,Vyacheslav Rovner,Lars W. Liebmann,Larry Pileggi,Andrzej J. Strojwas,Jason D. Hibbeler +5 more
TL;DR: This paper claims that a far superior result can be achieved by moving the design-to-manufacturing interface from design rules to a higher level of abstraction based on a defined set of pre-characterized layout templates and demonstrates how this methodology can simplify optical proximity correction and lithography processes for sub-32 nm technology nodes.
Proceedings ArticleDOI
Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded design
TL;DR: This paper proposes a novel algorithm to optimally assign cuts to 193i or E-Beam processes with proper modifications on cut distribution in order to maximize the overall throughput and shows that the throughput is dramatically improved by the cut redistribution.
Proceedings ArticleDOI
Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14 nm node
Kaushik Vaidyanathan,Siew Hoon Ng,Daniel H. Morris,Neal Lafferty,Lars W. Liebmann,Mitchell Bender,Wenbin Huang,Kafai Lai,Larry Pileggi,Andrzej J. Strojwas +9 more
TL;DR: Comparison of the design efficiency and manufacturability of standard cell libraries that use either unidirectional or bidirectional Metal 1 shows that a 14 nm 9-track uniddirectional standard cell layout results in up to 20% lower energy-delay-area product as compared to the 9- track bid DirectionalStandard cell layout.
Journal ArticleDOI
Detailed Routing Algorithms for Advanced Technology Nodes
Markus Ahrens,Michael Gester,Niko Klewinghaus,Dirk Muller,Sven Peyer,Christian Schulte,Gustavo E. Tellez +6 more
TL;DR: Algorithm for routing in advanced technology nodes, used by BonnRoute (BR) to obtain efficient and almost design rule clean wire packings and pin access solutions, and combines BR with an industrial router for cleaning up the remaining design rule violations.
Journal ArticleDOI
Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control
TL;DR: In this article, a shift-trim double-patterning lithography (ST-DPL) technique was proposed for achieving pitch relaxation with a single photomask, where the mask is re-used for the second exposure by applying a translational mask-shift.
References
More filters
Proceedings ArticleDOI
Layout impact of resolution enhancement techniques: impediment or opportunity?
TL;DR: This tutorial introduces the reader to the basic concepts of optical lithography, derives fundamental resolution limits, and explains the principles of resolution enhancement techniques and their impact on chip layout.
Proceedings ArticleDOI
Intel design for manufacturing and evolution of design rules
TL;DR: This paper will discuss the approach to DFM though co-optimization across design and process, where the poly layer is used to show how rules have changed to meet patterning requirements and how co- Optimization has been used to define the poly design rules.
Proceedings ArticleDOI
Convergent Automated Chip Level Lithography Checking and Fixing at 45nm
Valerio Perez,Shyue Fong Quek,Sky Yeo,Colin Hui,Kuang Kuo Lin,Walter Ng,Michel Luc Cote,Bala Kasthuri,Philippe Hurat,Matthew A. Thompson,Chi-Min Yuan,Puneet Sharma +11 more
TL;DR: This paper shows how a design-oriented litho model was built and used to automate a litho hotspot fixing design flow, and the guidelines to the fixing tools in an industry based integrated flow were fed.