Showing papers in "Journal of Micro-nanolithography Mems and Moems in 2007"

True process variation aware optical proximity correction with variational lithography modeling and model calibration

Abstract: Optical proximity correction (OPC) is one of the most widely used resolution enhancement techniques (RET) in nanometer designs to improve subwavelength printability. Conventional model-based OPC assumes nominal process conditions without considering process variations because of the lack of variational lithography models. A simple method to improve OPC results under process variations is to sample multiple process conditions across the process window, which requires long run times. We derive a variational lithography model (VLIM) that can simulate across the process window without much run-time overhead compared to the conventional lithography models. To match the model to experimental data, we demonstrate a VLIM calibration method. The calibrated model has accuracy comparable to nonvariational models, but has the advantage of taking process variations into consideration. We introduce the variational edge placement error (VEPE) metrics based on the model, a natural extension to the edge placement error (EPE) used in conventional OPC algorithms. A true process-variation aware OPC (PVOPC) framework is proposed used the VEPE metric. Due to the analytical nature of VLIM, our PVOPC is only about 2 to 3× slower than the conventional OPC, but it explicitly considers the two main sources of process variations (exposure dose and focus variations) during OPC. Thus our post-PVOPC results are much more robust than the conventional OPC ones, in terms of both geometric printability and electrical characterization under process variations.

Maximization of layout printability/manufacturability by extreme layout regularity

Abstract: In the past, complying with design rules was sufficient to ensure acceptable yields for a design. However, for sub-100-nm designs, this approach tends to create patterns that cannot be reliably printed for a given optical setup, thus leading to hot spots and systematic yield failures. Recent challenges faced by both the design and process communities call for a paradigm shift whereby circuits are constructed from a small set of lithography-friendly patterns that have previously been extensively characterized and ensured to print reliably. We describe the use of a regular design fabric for defining the underlying layout geometries of the circuit. While the direct application of this methodology to the current application-specific integrated circuit (ASIC) design flow would result in unnecessary area and performance penalties, we overcome these penalties via a unique design flow that ensures shape-level regularity by reducing the number of required logic functions as much as possible as part of the top-down design flow. We show that with a small set of Boolean functions and careful selection of lithography-friendly patterns, we not only mitigate but essentially eliminate such penalties. Additionally, we discuss the benefits of using extremely regular designs constructed from a limited set of lithography-friendly patterns not only to improve manufacturability but also to relax the pessimistic constraints defined by design rules. Specifically, we introduce the basis to exploit the regularity in the layout patterns by using "pushed-rules" for logic design, as is commonly done for static random access memory (SRAM). This in turn facilitates a common optical proximity correction (OPC) methodology for logic and SRAM. Moreover, by taking advantage of this newfound manufacturability and predictability of regular circuits, we show that the performance of logic built on regular fabrics can surpass that of seemingly more arbitrarily constructed logic.

Resolution Enhancement Techniques and Design for Manufacturability: Containing and Accounting for Variabilities in Integrated Circuit Creation

Abstract: This PDF file contains the editorial “Resolution Enhancement Techniques and Design for Manufacturability: Containing and Accounting for Variabilities in Integrated Circuit Creation” for JM3 Vol. 6 Issue 03

Progress on implementation of a reference measurement system based on a critical-dimension atomic force microscope

Abstract: The National Institute of Standards and Technology (NIST) and SEMATECH are working to address traceability issues in semiconductor dimensional metrology. In semiconductor manufacturing, many of the measurements made in the fab are not traceable to the SI unit of length. This is because a greater emphasis is often placed on precision and tool matching than on accuracy. Furthermore, the fast pace of development in the industry makes it difficult to introduce suitable traceable standard artifacts in a timely manner. To address this issue, NIST and SEMATECH implemented a critical-dimension atomic-force-microscope-based reference measurement system (RMS). The system is calibrated for height, pitch, and width, and has traceability to the SI definition of length in all three axes. Because the RMS is expected to function at a higher level of performance than inline tools, the level of characterization and handling of uncertain sources is on a level usually seen in instruments at national measurement institutes. In this work, we discuss recent progress in reducing the uncertainty of the instrument as well as details of a newly implemented performance monitoring system. We also present an example of how the RMS concept can be used in a semiconductor manufacturing environment.

Characterization study of bonded and unbonded polydimethylsiloxane aimed for bio-micro-electromechanical systems-related applications

Abstract: Authors have demonstrated that by controlling the mixing ratio of polydimethylsiloxane's (PDMS's) two components-base polymer (part A) and a curing agent (part B)-different mechanical properties of PDMS can be achieved. Test results show that the Young's modulus decreases as the increasing of mixing ratios (A:B). However, there is a transitional mixing ratio (part A:part B=10) after which the Young's modulus is almost independent of the mixing ratio. The PDMS's thickness plays an important role in determining the mechanical properties. The results show that the thinner the PDMS, the stiffer it behaves. The bonding strength between two cured PDMS parts with different mixing ratios shows that it depends on the mixing ratio. A maximum bonding strength of 130 kPa occurs on a bonded couple with mixing ratios of 30A:1B and 3A:1B, respectively. The fracture on bonded specimens does not occur at the bonding interfaces. Instead it occurs at the side with a larger portion of part A. The intermediate material property formed at the interface is attributed to the diffusion layer formed.

Versatile stepper based maskless microlithography using a liquid crystal display for direct write of binary and multilevel microstructures

Abstract: A versatile photolithographic photoplotter based on a stan- dard photoreduction stepper, where the reticle is replaced by a commer- cial liquid crystal microdisplay, is reported. The microdisplay module is designed as a drop-in replacement, allowing the photoplotter to be sim- ply and quickly converted into a standard stepper, making it an extremely versatile, low-cost research and development tool. Binary and multilevel plotting are demonstrated with plot rates of several Mpixels/s and 1-m feature sizes into standard industrial photoresist. The limitations on plot rate and resolution are presented and techniques for overcoming them discussed. © 2007 Society of Photo-Optical Instrumentation Engineers.

Rigorous electromagnetic field mask modeling and related lithographic effects in the low k1 and ultrahigh numerical aperture regime

Abstract: As smaller feature sizes and hyper-numerical apertures (>1.0) are approached, rigorous electromagnetic field (EMF) simulation of light diffraction from the mask predicts a more pronounced impact of the mask topography, the optical properties of the mask materials, and the polarization of the incident light on the resulting intensity and the phase of the diffracted light, and on the imaging performance of a lithographic process. This work applies rigorous EMF simulation for the exploration of several aspects of the imaging performance of different binary and 6% attenuated mask stacks at the limits of dry, water immersion, and high index or oil immersion lithography. Several consequences with respect to typical lithographic performance parameters are discussed. The described mask diffraction phenomena have a strong impact on the sensitivity of printed linewidths and process windows with respect to the illumination intensity in the preferred state (IPS) of polarization. Advanced diffraction phenomena are also shown to be important for the lithographic performance of assist features. A new metric, the so-called assist bending efficiency (ABEF), is proposed to quantify the related effects. Modifications of the phase of the diffracted light may result in placement errors and process-window deformations.

Double-exposure mask synthesis using inverse lithography

Abstract: Inverse lithography mask design and double-exposure lithog- raphy are two technologies that have gained a lot of attention in the recent past. Inverse lithography consists of synthesizing the input mask that leads to the desired output wafer pattern by inverting the mathemati- cal forward model from mask to wafer. Double-exposure lithography uses two pairs of mask and exposure to print a single desired wafer pattern. It usually involves splitting the latter into two parts. In this work, we present some preliminary results in our unique effort to combine the previous two powerful techniques. The goal is to use the inverse imaging approach to automatically synthesize the masks required to print the desired wafer pattern employing double-exposure lithography. We em- ploy the pixel-based mask representation, analytically calculate the gra- dient, and use a cyclic coordinate descent optimization algorithm to syn- thesize the two masks. We present results for chromeless phase-shift masks for an idealized case of a coherent imaging system =0 using the Kirchhoff approximation. The results indicate that our algorithm au- tomatically splits the target pattern into two overlapping parts, which are used separately during the individual exposures. Furthermore, the proposed approach is also capable of resolving the phase conflicts. The comparison with a single-exposure case indicates a superior contrast and no hot-spots. © 2007 Society of Photo-Optical Instrumentation Engineers.

Direct optimization approach for lithographic process conditions

Abstract: We present a semiautomatic procedure for the optimization of lithographic process conditions. In the regime of resolution enhancement techniques such as optical proximity correction, off-axis illumination, and phase shifting masks, the design of lithographic photomasks and illumination sources becomes increasingly intricate. Earlier "what you see is what you get" (WYSIWYG) approaches cannot be applied anymore. Instead, the employment of sophisticated design optimization tools is inevitable. In contrast to related efforts using an inverse problem formulation to address this goal, the approach presented here can be considered a direct method: mask and illumination layouts are mutually altered, evaluated, and improved, using an heuristic search algorithm. Thus, not only does this method require very little a priori knowledge of the process, it also allows for a very flexible problem formulation, enabling an easy integration of different model options or even process steps. As an underlying optimization algorithm of the presented procedure, a genetic algorithm has been used, whose flow, data representation, and basic operations are discussed briefly. Different representation types for both mask and illumination setups and the formulation of the optimization objectives are explained in detail. Various well-performing mask and illumination settings demonstrate the feasibility of the proposed approach and point out further potentials: in contrast to single problem specific approaches, this method is applicable to a great variety of different complex optimization tasks in advanced lithography.

Through-process modeling for design-for-manufacturability applications

Abstract: In recent years, design for manufacturability (DFM) has become an important focus item of the semiconductor industry and many new DFM applications have arisen. Most of these applications rely heavily on the ability to model process sensitivity, and here we explore the role of through-process modeling on DFM applications. Several different DFM applications are examined and their lithography model requirements analyzed. The complexities of creating through-process models are then explored, and methods to ensure their accuracy presented.

Ultra-high-resolution monolithic thermal bubble inkjet print head

Abstract: A monolithic inkjet print head, fabricated with silicon micromachining technology and capable of generating microscale liquid droplets, is developed and shown to function successfully. The print head uses a dense array of thermal bubble inkjet devices, made on a single silicon wafer. Each device is made of a Pt heater stack, a small, shallow fluid chamber, and a refilling channel formed by a Ge-sacrificial etching process, a deep-etched through-wafer feeding hole, and a micron-scale nozzle opened in a thin nitride membrane by plasma etching. Experimental results with a high resolution video imaging system show that this print head is capable of generating water droplets as small as 3 µm in diameter (0.014 pL), about 1/70th the volume of the droplets produced by existing inkjet systems. The printing process is also found to be stable, uniform in droplet size and velocity, and free of satellite droplets at optimum operation conditions. At small distances between the print head and substrate, droplet spreading is also small. This print head is then a capable tool for ultra-high-resolution inkjet printing and can be used in research areas where delivery of micron-scale fluid droplets is desired.

Effects of fast secondary electrons to low-voltage electron beam lithography

Abstract: In 1981 A. N. Broers suggested that the spatial limit of direct writing electron beam lithography (DWEBL) would be limited to ~10 nm by the laterally scattered fast secondary electrons (FSE) even in atomically thin resist. One possible solution to this restriction would be to use low- or ultralow-energy electrons. Experiments and simulations have been carried out to quantify the contribution of FSE to the energy deposition that results in exposure of the resist over high-beam energies. To examine the effects of FSE on low-voltage operations, studies of electron-beam lithography (EBL) in the low- to ultralow-energy range, employing commonly used resists such as PMMA, were performed, and the results were compared to those from conventional high-voltage processing. DWEBL was performed in a Schottky field emission gun scanning electron microscope (SEM), used in cathode-lens mode for ultralow-voltage operation. The exposure characteristics and sensitivity of the system at these energies have been investigated using Monte Carlo simulation methods. Saturation doses were calculated at low energies, which would give a useful condition to target for routine exposure because it ensures the critical dimensions will not be affected by any random changes in beam intensity.

Reduced complexity compression algorithms for direct-write maskless lithography systems

Abstract: Achieving the throughput of one wafer layer per minute with a direct-write maskless lithography system, using 22-nm pixels for 45-nm feature sizes, requires data rates of about 12 Tb/s. In our previous work, we developed a novel lossless compression technique specifically tailored to flattened, rasterized, layout data called context copy combinatorial code (C4), which exceeds the compression efficiency of all other existing techniques including BZIP2, 2D-LZ, and LZ77, especially under a limited decoder buffer size, as required for hardware implementation. In this work, we present two variations of the C4 algorithm. The first variation, block C4, lowers the encoding time of C4 by several orders of magnitude, concurrently with lowering the decoder complexity. The second variation, which involves replacing the hierarchical combinatorial coding part of C4 with Golomb run-length coding, significantly reduces the decoder power and area as compared to block C4. We refer to this algorithm as block Golomb context copy code (block GC3). We present the detailed functional block diagrams of block C4 and block GC3 decoders, along with their hardware performance estimates as the first step of implementing the writer chip for maskless lithography.

Complementary dose and geometrical solutions for electron beam direct write lithography proximity effects correction: application for sub-45-nm node product manufacturing

Abstract: After the successful results obtained in the last few years, electron beam direct write (EBDW) lithography for use in integrated circuit manufacturing has now been demonstrated. However, throughput and resolution capabilities need to be improved to push its interest for fast cycle production and advanced research and development applications. In this way, the process development needs good patterns dimensional accuracy, i.e., a better control of the proximity effects caused by backscattering electrons and others phenomenon. In this work, the limitations of the dose modulation method are investigated through the change of dose number steps and the use of a more accurate point spread function. To continue reducing feature sizes, a method to provide a complementary correction to the dose modulation solution is proposed. This rule-based electron beam proximity correction, or REBPC, provides good results down to 40 nm.

Performance-driven optical proximity correction for mask cost reduction

Abstract: With continued aggressive process scaling in the subwavelength lithographic regime, resolution enhancement techniques (RETs) such as optical proximity correction (OPC) are an integral part of the design to mask flow. OPC creates complex features to the layout, resulting in mask data volume explosion and increased mask costs. Traditionally, the mask flow has suffered from a lack of design information, such that all features (whether critical or noncritical) are treated equally by RET insertion. We develop a novel minimum cost of correction (MinCorr) methodology to determine the level of correction of each layout feature, such that prescribed parametric yield is attained with minimum RET cost. This flow is implemented with model-based OPC explicitly driven by timing constraints. We apply a mathematical-programming-based slack budgeting algorithm to determine OPC level for all polysilicon gate geometries. Designs adopted with this methodology achieve up to 20% Manufacturing Electron Beam Exposure System (MEBES) data volume reduction and 39% OPC run-time improvement.

Dry etching for the correction of gap-induced blurring and improved pattern resolution in nanostencil lithography

Abstract: We present nanostencil lithography as a new and parallel nanopatterning technique for batch fabrication of micro/nanoelectromechanical systems (MEMS/NEMS) with high throughput and resolution. We use nanostencil lithography for the purpose of integrating nanomechanical resonators into complementary metal-oxide semiconductor (CMOS) circuits. When patterning nonflat substrates, which is the case of CMOS wafers, the gap between the nanostencil membrane and the surface induces a pattern blurring that constitutes an intrinsic limitation to the maximum achievable resolution. In our case, the lateral blurring is on the order of 150 nm on each side. We present here a remedy to this limitation that is based on a corrective dry etching step that removes the excess material and which recovers the designed pattern dimensions. As a demonstration, we succeed in the patterning of an entire 100-mm-diam wafer with nanomechanical devices having lateral dimensions in the range of 200 nm.

Microchannels with rectangular and arched core shapes fabricated using sacrificial etching

Abstract: A study of relevant fabrication parameters is presented for a process that uses chemical etching of sacrificial cores to produce long, hollow microchannels. Two different sacrificial materials are investigated, SU8 and reflowed photoresist. These two materials produce channel cross sections with rectangular and arch-shaped cores, respectively. Fabrication times based on etch removal rates of sacrificial materials are reported for SU8 core microchannels and for a hybrid core consisting of reflowed photoresist and aluminum layers. The hybrid design takes advantage of the fast etch times possible for aluminum, but also produces smooth, arched sidewalls. Structural integrity is also investigated for different microchannels, specifically the wall thickness required to produce an intact channel of a given width. Empirical design rules indicate that SU8-based core channels require a wall thickness-to-width ratio of greater than 1:10, and reflowed photoresist based structures require a ratio greater than 1:50.

Laterally actuated multicontact MEMS relay fabricated using MetalMUMPS process: experimental characterization and multiscale contact modeling

Abstract: Multicontact MEMS relays laterally actuated using electrostatic comb-drive actuators are reported. The relay consists of a movable main beam anchored to the substrate using two identical folded suspension springs. Multicontact RF ports consist of five movable fingers connected to the movable main beam and six fixed fingers anchored to the substrate. Comb-drive actuators located at the top and bottom ends of the main beam enable bidirectional actuation of the RF contacts. The MEMS relays were fabricated using the MetalMUMPs process, which uses 20-µm-thick electroplated nickel as the structural layer. A 3-µm-thick gold layer was electroplated at the electrical contact surfaces. An example MEMS relay with planar contacts of area 80 µm×20 µm and a spacing of 10 µm between the movable and fixed contacting surfaces is discussed. The overall size of the relay is approximately 3 mm×3 mm. "Resistance versus applied voltage" characteristics of the MEMS relay have been measured for applied DC bias voltages in the range of 172 V to 220 V. A multiscale rough surface contact model was used to estimate the actual electrical contact resistance versus applied force curve of these devices. The multiscale model showed good qualitative agreement with the experimental measurements but requires more refinement to achieve good quantitative agreement.

Study of stress and adhesion strength in SU-8 resist layers on silicon substrate with different seed layers

Abstract: We present the details of our study on the internal stresses and adhesion strengths of SU-8 structures to different substrate seed layers. The effect of adhesion promoter-methacryloxy [propl] trimethoxysilane (MPTS), and OmniCoat-and different seed layer combinations (Ti/Cu/Ti, Ti/Cu, Cr/Au, and Cr/Au/Cr) was examined for internal stress and adhesion strength in 650-µm-thick SU-8 films. Increased stress and poor adhesion have led to the delamination of SU-8 in some cases. Adhesion and stress have proven to be the function of process parameters such as soft bake (time and temperature), exposure dose, post-exposure bake (time and temperature), and development time. We have found that a 100 silicon wafer containing a titanium-copper-titanium (Ti/Cu/Ti) seed layer with MPTS as the adhesion promoter yielded a thick SU-8 film with a lower value of stress and consequently better adhesion for processing in deep x-ray lithography (DXRL). A detailed correlation of the effects of adhesion and internal stress on the SU-8 film is discussed. An analysis of the possible chemical bonding interactions occurring between SU-8, and its adhesion promoter and/or substrate is also presented.

Nanoscale thermal lithography by local polymer decomposition using a heated atomic force microscope cantilever tip

Abstract: Nanopatterning of polymer thin films is the basis for the vast majority of current microlithography processes used in integrated circuit manufacturing. Future scaling of such polymer patterning methods will require innovative solutions to overcome the prohibitively high tool and mask costs associated with current optical lithography methods, which will prevent their use in many applications. Scanning probe-based methods for surface modification are desirable in that they offer high resolution patterning while also offering the ability to perform in situ metrology. We report a new scanning probe lithography method that uses heated atomic force microscope cantilevers to achieve nanoscale patterning in thin polymer films via the local thermal decomposition of the polymer and in situ postdecomposition metrology. Specifically, cross-linked polycarbonate thin films are developed in this work and are shown to be excellent writing media for this process. This new method has the advantage that the tip can be heated and cooled on microsecond time scales and thus material can be removed and patterned without need for the disengagement of the tip from the polymer surface. This ability to write while the tip is constantly engaged to the surface offers significantly higher writing speeds for discontinuous patterns relative to other scanning probe techniques.

Exposure dose dependence on line edge roughness of a latent image in electron beam/extreme ultraviolet lithographies studied by Monte Carlo technique

Abstract: Of great importance in post-optical lithographies, such as electron beam (EB) and extreme ultraviolet, is the improvement of line edge roughness or line width roughness of patterned resists. We provide an exposure dose dependence on LER of a latent image in chemically amplified EB resist from 1 to 50 µC/cm2. By using a Monte Carlo simulation and empirical equations, the effects of exposure dose and amine concentration on LER are investigated in terms of shot noise and image contrast. We make clear the correlation between LER and the fluctuation of the initial number of acid molecules generated in resists.

Impact of photoresist composition and polymer chain length on line edge roughness probed with a stochastic simulator

Abstract: The impact of various parameters such as photoacid generator (PAG) concentration, acid diffusion length, and polymer size on the finally obtained line edge roughness (LER) in chemically amplified photoresists are investigated with a stochastic simulator. A new aspect of the simulations is to start with a polymer matrix modeled by molecular dynamics simulation and subsequently simplify the description of the resist composition for mesoscopically simulating the post-exposure bake (PEB) and development steps. The results show that decreasing the molecular weight (MW) of chain-like polymers does not necessarily lead to lower roughness values. Acid-breakable polymers are simulated as well showing that they can lead to improved LER characteristics.

Modeling and optimization of debris mitigation systems for laser and discharge-produced plasma in extreme ultraviolet lithography devices

Abstract: Physical models are developed to investigate the following conditions relevant to discharge-produced plasma (DPP) devices under development for extreme ultraviolet (EUV) lithography: gaseous jet propagation in the chamber, removal of neutral particles with a gaseous jet, and deviation of charged particles with a magnetic field. Several geometries of the mitigation systems are considered for removing debris during the EUV lithographic process. The design of a mitigation system is proposed and simulated with the computer models. The behavior of Xe, Li, and Sn debris in Ar and He jets is simulated by using the high energy interaction with general heterogeneous target systems (HEIGHTS) integrated package. Final energy and local distributions are calculated using experimental debris data from current EUV facilities.

Parameter extraction from simple electrical measurements on surface micromachined cantilevers

Abstract: In surface micromachined structures, many parameters like geometry and Young's modulus depend on the process steps and need to be measured for accurate prediction of their functionality. This work discusses simple electrical measurement techniques on surface micromachined cantilever beams to determine Young's modulus, the gap between the beam and the substrate, and the thickness of a deposited aluminum layer on the beam. Cantilevers are ubiquitous in most microelectromechanical system (MEMS) sensors and actuators, and hence are ideal test structures. Pull-in, and a novel resonance frequency measurement based on the pull-in technique, are done on oxide anchored doped polysilicon beams at the wafer level, and some of the device and material properties are extracted from these measurements. The extracted values are compared with those determined from established methods like vibrometry and surface profiler measurements, and show good agreement. Since the measurements are all electrical, they can be part of standardized testing and are also suitable for packaged devices.

Automated hot-spot fixing system applied to the metal layers of 65-nm logic devices

Abstract: Hot-spot clearance using process simulation is indispensable for low-k1 lithography processes. Hot spots will occur mainly depending on local pattern context. Appropriate calibration of design rules, mask data preparation, resolution enhancement techniques, and optical proximity effect correction will reduce potential hot spots. However, pattern layout variety is so enormous that, even with the most careful calibration of every process, an unexpected potential hot spot is occasionally left in the design layout. Manual modification of the design at the hot spot will be effective, but it takes too much time. Therefore, there is a need for an automated hot-spot fixing system so as to avoid fatal hot-spot occurrence, with sufficient process margins and short turnaround time. We developed an automated hot-spot fixing system, the hot-spot fixer (HSF). Design data is automatically modified according to the instruction at every hot spot, complying with the design rule. We applied the HSF system to the metal layer of logic devices of 65 nm and most of the hot spots were diminished throughout a full chip within 12 hours. Thus, HSF feasibility has been proved for metal layers in the 65-nm node and below with full-chip data volume.

Photolithographic patterning of bihelical tracks onto conical substrates

Abstract: We demonstrate the direct photolithographic patterning of a grossly nonplanar substrate by creating 62-m helical tracks on a 22- mm-high cone. The projection of focused light onto the 3-D surface is achieved using a computer-generated hologram CGH suitably illumi- nated so as to create the required pattern on the photoresist-coated surface. The approach adopted forms the basis of a novel method for patterning nonplanar structures. We address the key challenges encoun- tered for the implementation of holographic photolithography in three dimensions, including mask design and manufacture, exposure compen- sation, mask alignment, and chemical processing. Control of linewidth and resolution over the nonplanar surface is critical. We describe the methods adopted and critically assess the structures created by this pro- cess. The bihelical cone is representative of a broadband, high- frequency coil-like structure, known in wireless communications as a log- periodic antenna. © 2007 Society of Photo-Optical Instrumentation Engineers.

Micro–Rayleigh-Bénard convection polymerase chain reaction system

Abstract: Polymerase chain reaction (PCR) is a molecular biological method for in vitro amplification of nucleic acids. Our objective was to design a micro-PCR system that included a Rayleigh-Benard convection PCR chip, measurement circuits, and circuits to control the temperature. A Rayleigh-Benard convection PCR chip was easily fabricated by using microelectromechanical system technology, and the sample solution could be put in to finish the completed PCR cycling within several minutes. The flow stream, velocity, and temperature profile in a micro-PCR system are important to achieve the successful PCR, but they are not easily observed with an experimental method. Thus, a CFDRC simulation of Rayleigh-Benard convection PCR was undertaken to determine the above important parameters. The duration of one cycle, the extension time, and total duration of 25 cycles can be calculated to achieve the optimal design. Finally, using agarose-gel electrophoresis, we verified the practicability of this system. The comparison study of PCR experiments performed with a commercial PCR machine and our chips showed that our chips can greatly decrease the duration of the reaction. By comparing the simulation and PCR experiment results with varied designed sizes, a user can set the parameters and computational fluid dynamics results for optimal designs and decrease the total duration of future reactions.

Micro angular rate sensor design and nonlinear dynamics

Abstract: We present an innovative micro gyroscope that is capable of detecting three-dimensional (3-D) angular motions. The motion of each sensing element is, by mechanical design, restricted to move in a direction orthogonal to each other such that measurements by high-resolution capacitors with signal processing circuits are decoupled and precisely represent, to some extent, angular velocity components in three axes. In order to ensure better repeatability and more reliability, the suspension flexures and stiffness are studied such that the stress of the proposed micro gyroscope is reduced, but the stroke of angular displacements is increased. Owing to the complicated geometry of the suspension flexures, the finite element method (FEM) is employed to obtain more exact stiffness value and compared with theoretical analysis. The dynamic model of the proposed gyroscope is established to include nonlinear terms and gyroscopic effects. The entire micro device can be produced merely by surface micromachining and wet etching such that the mass production cost has been considered at the design stage but the resolution, bandwidth, and decoupling capability of tri-axis detection are expected to be enhanced.

Limiting factors for electron beam lithography when using ultra-thin hydrogen silsesquioxane layers

Abstract: Isolated dots and lines with 6 nm width are written in 20-nm-thick hydrogen silsesquioxane (HSQ) layers on silicon substrates, using 100-keV electron beam lithography. The main factors that might limit the resolution, i.e., beam size, writing strategy, resist material, electron dose, and development process, are discussed. We demonstrate that, by adjusting the development process, a very high resolution can be obtained. We report the achievement of 7 nm lines at a 20-nm pitch written in a 10-nm-thick HSQ layer, using a potassium-hydroxide (KOH)-based developer instead of a classical tetra-methyl-ammonium hydroxide (TMAH) developer. This is the smallest pitch achieved to date using HSQ resist. We think that the resolution can be improved further, and is presently limited by either the beam diameter (which was not measured separately) or by the not-fully-optimized development process.

Measuring thin film elastic modulus using a micromachined cantilever bending test by nanoindenter

Abstract: It is convenient to characterize thin film material properties using commercially available nanoindentation systems. This study aims to discuss several considerations while determining the thin film elastic modulus by means of a microcantilever bending test using a commercial nanoindentation system. The measurement results are significantly improved after: 1. the indentation of the film during the test is considered and corrected, and 2. the boundary effects are considered in the model by finite element method. In application, the elastic modulus of electroplating nickel film 11 µm thick was characterized.