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Proceedings ArticleDOI

SRP: simultaneous routing and placement for congestion refinement

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TLDR
An effective simultaneous routing and placement refinement tool called SRP is proposed for routability improvement, independent of any placer and global router, and can reduce the overflow effectively.
Abstract
In this paper, an effective simultaneous routing and placement refinement tool called SRP is proposed for routability improvement. SRP is independent of any placer and global router. Based on a given placement layout and global routing result, SRP relocates problematic cells by considering routing and placement simultaneously. Not only overflow from local nets, but overflow from global and semi-global nets can be solved by SRP. A cell will be relocated and its associated nets will be rerouted if its connections go across any congested region, even if the cell is not in the congested region. Therefore, our method can reduce the overflow effectively. Given the layouts generated by the top four routability-driven placers in the DAC Contest 2012, our method can still reduce the total overflow by 32.6% in average while the routed wirelength and HPWL are not increased obviously.

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Proceedings ArticleDOI

Ripple 2.0: high quality routability-driven placement via global router integration

TL;DR: This paper presents a high quality placer Ripple 2.0 to solve the routability-driven placement problem and proposes several techniques, including lookahead routing analysis with pin density consideration, routing path-based cell inflation and spreading and robust optimization on congested cluster.
Proceedings ArticleDOI

POLAR 2.0: An Effective Routability-Driven Placer

TL;DR: A new placer POLAR 2.0 is proposed emphasizing both approaches to minimizing the routing demand and maintaining a good wirelength-driven placement in the global placement stage, and outperforms all published academic routability-driven placers both in runtime and quality.
Proceedings ArticleDOI

Closing the Gap between Global and Detailed Placement: Techniques for Improving Routability

TL;DR: This work proposes a placement framework that offers a complete coverage solution in considering both global and detailed routing congestion, and a placement migration strategy is proposed, which improvesDetailed routing congestion while preserving the placement integrity that is optimized for global routability.
Journal ArticleDOI

Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement

TL;DR: A routability-driven placer, Ripple 2.0, is presented, which emphasizes both kinds of routing congestion and achieves a better detailed routing solution obtained by a commercial router.
References
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Proceedings ArticleDOI

mPL6: enhanced multilevel mixed-size placement

TL;DR: The multilevel placement package mPL6 combines improved implementations of the global placer mPL5 and the XDP legalizer and detailed placer and the ASPDAC06 and consistently produces robust, high-quality solutions to difficult instances of mixed-size placement in fast and scalable run time.
Journal ArticleDOI

Implementation and extensibility of an analytic placer

TL;DR: It is empirically demonstrated that the APlace framework is a general, and extensible platform for "spatial embedding" tasks across many aspects of system physical implementation.
Proceedings ArticleDOI

Implementation and extensibility of an analytic placer

TL;DR: It is empirically demonstrated that the APlace framework is a general, and extensible platform for "spatial embedding" tasks across many aspects of system physical implementation.
Proceedings ArticleDOI

FastRoute: a step to integrate global routing into placement

TL;DR: An extremely fast and high-quality global router called FastRoute is presented that incorporates global routing directly into placement process without much runtime penalty and will fundamentally change the way the EDA community look at and make use of global routing in the whole design flow.
Proceedings ArticleDOI

An effective congestion driven placement framework

TL;DR: A fast but reliable way to detect routing criticalities in VLSI chips by using a congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm.
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