Submicrometer polysilicon gate CMOS/SOS technology

TLDR: In this article, a process for the fabrication of CMOS/SOS submicrometer devices and integrated circuits is described, which utilizes the lateral diffusion of boron into polycrystalline silicon and a subsequent anisotropic etchant to define the narrow poly gates.

Abstract: A process is described for the fabrication of CMOS/SOS submicrometer devices and integrated circuits. The process utilizes the lateral diffusion of boron into polycrystalline silicon and a subsequent anisotropic etchant to define the narrow poly gates. Devices with channel lengths as small as 0.3 µm have been fabricated and characterized. Both avalanche and tunnel injection of carriers into the gate dielectric have been measured and both can have an impact on the limit of voltage operation. At present, these mechanisms appear to place an upper limit of about 8 V on the operating voltage of dynamic circuits containing 0.5- µm channel length devices. The propagation delay of 0.5-µm channel length CMOS/SOS inverters is about 200 ps at 5 V and dynamic binary counters will operate with a maximum input frequency of 550 MHz and 8 V while dissipating 130 mW.