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Journal ArticleDOI

Temporal partitioning and scheduling data flow graphs for reconfigurable computers

K.M.G. Purna, +1 more
- 01 Jun 1999 - 
- Vol. 48, Iss: 6, pp 579-590
TLDR
The concept of temporal partitioning to partition a task into temporally interconnected subtasks and proper scheduling followed by proper scheduling can facilitate the configurable computer based execution are introduced.
Abstract
FPGA-based configurable computing machines are evolving rapidly. They offer the ability to deliver very high performance at a fraction of the cost when compared to supercomputers. The first generation of configurable computers (those with multiple FPGAs connected using a specific interconnect) used statically reconfigurable FPGAs. On these configurable computers, computations are performed by partitioning an entire task into spatially interconnected subtasks. Such configurable computers are used in logic emulation systems and for functional verification of hardware. In general, configurable computers provide the ability to reconfigure rapidly to any desired custom form. Hence, the available resources can be reused effectively to cut down the hardware costs and also improve the performance. In this paper, we introduce the concept of temporal partitioning to partition a task into temporally interconnected subtasks. Specifically, we present algorithms for temporal partitioning and scheduling data flow graphs for configurable computers. We are given a configurable computing unit (RPU) with a logic capacity of S/sub RPU/ and a computational task represented by an acyclic data flow graph G=(V, E). Computations with logic area requirements that exceed S/sub RPU/ cannot be completely mapped on a configurable computer (using traditional spatial mapping techniques). However, a temporal partitioning of the data flow graph followed by proper scheduling can facilitate the configurable computer based execution. Temporal partitioning of the data flow graph is a k-way partitioning of G=(V, E) such that each partitioned segment will not exceed S/sub RPU/ in its logic requirement. Scheduling assigns an execution order to the partitioned segments so as to ensure proper execution. Thus, for each segment in {s/sub 1/,s/sub 2/,...,s/sub k/}, scheduling assigns a unique ordering S/sub i/-j,1/spl les/i/spl les/k,1/spl les/j/spl les/k, such that the computation would execute in proper sequential order as defined by the flow graph G=(V, E).

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Citations
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Journal ArticleDOI

Reconfigurable computing: a survey of systems and software

TL;DR: The hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling are explored, and the software that targets these machines is focused on.
Journal ArticleDOI

Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks

TL;DR: This paper focuses on a runtime system for guarantee-based scheduling of hard real-time tasks, formulate the scheduling problem for the 1D and 2D resource models and present two heuristics, the horizon and the stuffing technique, to tackle it.
Journal ArticleDOI

Reconfigurable computing systems

TL;DR: The main focus of the paper is on outlining the methodologies required to realize the potential of reconfigurable architectures for vision applications and the development of fundamental configurable computing models that abstract the underlying hardware for high-level application mapping.
Book

Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications

TL;DR: The introduction and the conclusion are the main chapters of the book, which provide a very strong theoretical and practical background to the field of reconfigurable computing, from the early Estrins machine to the very modern architecture like coarse-grained reconfigured device and the embedded logic devices.
Journal ArticleDOI

Constraints-driven scheduling and resource assignment

TL;DR: A new method for modeling and solving different scheduling and resource assignment problems that are common in high-level synthesis (HLS) and system- level synthesis and developed in Java a constraint solver engine, JaCoP (Java Constraint Programming), to evaluate this approach.
References
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TL;DR: This paper presents a methodology for High-Level Synthesis of Architectural Models in Synthesis and its applications in Design Description Languages and Design Representation and Transformations.
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Force-directed scheduling for the behavioral synthesis of ASICs

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