Journal ArticleDOI
High-speed compact circuits with CMOS
TLDR
A new circuit type, the CMOS domino circuit, is described, which involves the connection of dynamic CMOS gates in such a way that a single clock edge can be used to turn on all gates in the circuit at once.Abstract:
Characteristics of various CMOS and NMOS circuit techniques are described, along with the shortcomings of each. Then a new circuit type, the CMOS domino circuit is described. This involves the connection of dynamic CMOS gates in such a way that a single clock edge can be used to turn on all gates in the circuit at once. As a result, complex clocking schemes are not needed and the full inherent speed of the dynamic gate can be utilized. The circuit is most valuable where gates are complex and have high fan-out such as in arithmetic units. Examples are shown of the use of domino circuits in an 8-bit ALU, where simulations indicate a speed advantage of 1.5 to 2 over traditional circuits, and in a 32-bit ALU where a worst case add in 124 ns was projected and a time less than 100 ns was achieved.read more
Citations
More filters
Proceedings ArticleDOI
Cascode voltage switch logic: A differential CMOS logic family
TL;DR: A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described.
Journal ArticleDOI
NORA: a racefree dynamic CMOS technique for pipelined logic structures
N.F. Goncalves,H. De Man +1 more
TL;DR: A new dynamic CMOS technique which is fully racefree, yet has high logic flexibility, and logic inversion is provided, which means higher logic flexibility and less transistors for the same function.
Journal ArticleDOI
Top-down pass-transistor logic design
TL;DR: The results show that the area, delay, and power dissipation are improved by LEAP and that the value-cost ratio is improved by a factor of three, demonstrating that LEAP has the potential to achieve a quantum leap in value of LSI's while reducing the cost.
Journal ArticleDOI
An entropy coding system for digital HDTV applications
S.-M. Lei,Ming-Ting Sun +1 more
TL;DR: A parallel structured VLC decoder which decodes each codeword in one clock cycle regardless of its length is introduced and the required clock rate of the decoder is lower, and parallel processing architectures become easy to adopt in the entropy coding system.
Journal ArticleDOI
Skew-tolerant domino circuits
David Harris,Mark Horowitz +1 more
TL;DR: Self-timed techniques eliminate clocks and clock skew but raise new issues of control overhead, timing assumption verification, and testability, which boosts operating frequency by tolerating clock skew, eliminating latches from the critical path, and better balancing logic between phases of the pipeline.
References
More filters
Mos integrated circuits.
TL;DR: In this article, an optimum structure for obtaining complementary regions of p-type and n-type silicon is given, where complementary pairs of normally off n-channel and p-channel devices were obtained both on separate and on a single substrate material.
Proceedings ArticleDOI
A CMOS 32b single chip microprocessor
TL;DR: A FULL 32b CPl* implemented in CMOS using a latc.h-up free twin-tub technology will be described, citing the architecture from both the user's external and internal hardware viewpoints.
Journal ArticleDOI
A design of CMOS polycell for LSI circuits
TL;DR: In this article, the authors designed polycells with a uniform height for LSI random logic circuits to minimize the product of propagation delay and chip area while allowing noise margins to be at least 25 percent of Vdd.
Proceedings ArticleDOI
A CMOS microprocessor for telecommunications applications
TL;DR: An 8-bit microprocessorX fabricated with a silicon-gate CMOS technology and packaged in a 40-pin DIP embodies several architectural innovations and an extended instruction set affording exceptional computing power.
Related Papers (5)
NORA: a racefree dynamic CMOS technique for pipelined logic structures
N.F. Goncalves,H. De Man +1 more