Patent
Transistor manufacturing process using three-step base doping
Jan L. De Jong,Jacob G. DeGroot +1 more
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In this article, the use of a three-step base doping technique enables the characteristics of a vertical bipolar transistor to be controllably reproduced at highly optimal values from run to run.Abstract:
In a transistor fabrication process, the use of a three-step base doping technique enables the characteristics of a vertical bipolar transistor to be controllably reproduced at highly optimal values from run to run. Insulating spacers (52A) are employed in forming a self-aligned base contact zone (58B). A shallow emitter (46) is created by outdiffusion from a patterned non-monocrystalline semiconductor layer (38A) that serves as the emitter contact. The fabrication process is compatible with the largely simultaneous manufacture of an insulated-gate field-effect transistor of the lightly doped drain type.read more
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Transistor with low resistance tip and method of fabrication in a CMOS process
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Method for fabricating a semiconductor device
TL;DR: In this article, an external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate, and then when the substrate is peeled, the support returns into the original shape by the restoring force and the peeled layer as well is curved along the shape of the support.
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Fabrication of bipolar transistors using selective doping to improve performance characteristics
TL;DR: In this paper, a vertical bipolar transistor is equipped with extra doping in the collector and in the base to improve the transistor's breakdown voltage and leakage current characteristics, which increases the cutoff frequency and overall current gain.
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Method of fabricating a miniaturized heterojunction bipolar transistor
Toshihiko Hamasaki,Hideki Satake +1 more
TL;DR: In this paper, the authors proposed a method of fabricating the transistor, which includes the steps of forming a first semiconductor layer of a first conductivity type on a substrate, and etching an unnecessary portion of the first semiconducting layer to form a groove, and burying an insulating layer in the groove, forming a second semiconductor layers serving as a base layer on the substrate and forming a third semiconductor board serving as an emitter.
References
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Patent
Manufacture of semiconductor device
TL;DR: In this article, a punching machine is used to cut a part of a resin tape body at the outside of a slit hole to prevent the insertion of an external force, such as bending or the like.
Patent
Process for forming TiSi2 layers of differing thicknesses in a single integrated circuit
TL;DR: In this paper, an integrated circuit may be fabricated providing refractory metal silicide layers, such as TiSi2, of differing thicknesses to provide optimal reductions in the sheet resistances of the regions in which refractories are formed.
Patent
Semiconductor planarization process and structures made thereby
TL;DR: In this article, a silicon substrate having a silicon dioxide bird's head is provided, where a thermal oxide layer is grown on the exposed silicon surface and a layer of phosphogermanosilicate glass is deposited on the thermal oxide and on the silicon dioxide head.
Proceedings ArticleDOI
2 Micron merged bipolar-CMOS technology
A.R. Alvarez,P. Meller,B. Tien +2 more
TL;DR: In this paper, a 2 µm process, merging the major technologies required to fabricate VLSI MOS and bipolar transistors on the same integrated circuit, is described.
Journal ArticleDOI
An advanced bipolar transistor with self-aligned ion-planted base and W/poly emitter
TL;DR: In this paper, an ion-implanted extrinsic base with a low sheet resistance of 55 Omega /square and a junction depth of 0.35 mu m is obtained using rapid thermal annealing.