Patent
Transistor sidewall spacer stress modulation
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TLDR
In this article, the spacer film is modulated to break at least some of the silicon nitride bonds, which can be performed selectively or non-selectively either before or after etching the film.Abstract:
A semiconductor fabrication process and the resulting integrated circuit include forming a gate electrode ( 116 ) over a gate dielectric ( 104 ) over a semiconductor substrate ( 102 ). A spacer film ( 124 ) exhibiting a tensile stress characteristic is deposited over the gate electrode ( 116 ). The stress characteristics of at least a portion of the spacer film is then modulated ( 132, 192 ) and the spacer film ( 124 ) is etched to form sidewall spacers ( 160, 162 ) on the gate electrode sidewalls. The spacer film ( 124 ) is an LPCVD silicon nitride in one embodiment. Modulating ( 132 ) the spacer film ( 124 ) includes implanting Xenon or Germanium into the spacers ( 160 ) at an implant energy sufficient to break at least some of the silicon nitride bonds. The modulation implant ( 132 ) may be performed selectively or non-selectively either before or after etching the spacer film ( 124 ).read more
Citations
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Semiconductor Device and Method for Fabricating the Same
TL;DR: In this article, a gate spacer is formed on a sidewall of the recess gate and an insulating film is selectively etched to form a landing plug contact hole, which is then filled with a conductive layer.
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Method of forming a locally strained transistor
TL;DR: In this paper, the authors proposed a semiconductor fabrication method based on PMOS and NMOS channel regions for improving their respective carrier mobility, where a highly stressed layer is deposited over the device and the stress is selectively adjusted in that portion of the layer over the gate electrode and the sidewall spacers.
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Method of fabricating strain-silicon CMOS
Deepak Kumar Nayak,Yuhao Luo +1 more
TL;DR: In this article, the first and second recesses are filled with a stressed material to induce strain in the channel, thereby improving carrier mobility, and the widths and depths of the second and third recesses can be selectable to optimize strain in channel region.
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Methods of fabricating semiconductor devices
TL;DR: In this paper, a silicon-germanium layer is formed on the PMOS transistor region, and nitrogen atoms are injected into the upper portion of the silicon Germanium layers before forming the first gate dielectric layer.
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Embedded stressor structure and process
TL;DR: In this article, a gate structure over a first region in a substrate is provided, and isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate.
References
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Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers
TL;DR: In this article, a process for using a silicon layer as an implant and out-diffusion layer, for forming defect-free source/drain regions in a semiconductor substrate, and also for subsequent formation of silicon nitride spacers is described.
Patent
Strained silicon layer semiconductor product employing strained insulator layer
TL;DR: In this paper, a strained silicon-germanium alloy material layer is formed upon a relaxed material substrate, which provides increased fabrication options which provide for enhanced fabrication efficiency when fabricating the strained silicon layer fabrication.
Patent
Method of making semiconductor structure with germanium implant for reducing short channel effects and subthreshold current near the substrate surface
TL;DR: In this article, a semiconductor structure with germanium implant is provided for reducing VT shifts at the channel edges thereby minimizing short channel effects and subthreshold currents at or near the substrate surface.
Patent
SOI MOSFET having amorphized source drain and method of fabrication
TL;DR: In this paper, a first and a second MOSFET are provided such that one of a source and a drain of the first MOSFLET is disposed adjacent one of the source and drain of a second mOSFLT.