Proceedings ArticleDOI
Trends toward spatial computing architectures
André DeHon
- pp 362-363
TLDR
The peak computational density for FPGAs shows at least a 10/spl times/ gap in raw density between processor architectures and FPG as, and what this means for the design of postfabrication, programmable computing devices.Abstract:
Describes the peak computation offered per unit silicon for RISC processors and FPGAs over the past two decades. Advances in processor architecture allow turning additional silicon area into additional performance. The time unit (seconds) is absolute, not normalized to process, so this represents some actual sacrifice of the increasing capabilities provided by the fabrication process to the design process, more complicated architectures, and increasing memory imbalance. The peak computational density for FPGAs shows at least a 10/spl times/ gap in raw density between processor architectures and FPGAs. The author assesses what this shows and what it means for the design of postfabrication, programmable computing devices.read more
Citations
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Proceedings ArticleDOI
Smart Memories: a modular reconfigurable architecture
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DPGA Utilization and Application
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Journal ArticleDOI
Fundamental Underpinnings of Reconfigurable Computing Architectures
TL;DR: This paper identifies the major parameters that distinguish architectures in this design space and draws connections between these parameters and physical requirements and application characteristics and identifies the fundamental advantages that reconfigurable architectures can offer.
Journal ArticleDOI
System-on-chip design: impact on education and research
TL;DR: The research center's goal will be to perform cross-disciplinary system design research to create new methodologies, tools, libraries, and courses-distributed via the Internet-to produce enough SOC architects worldwide.
Proceedings ArticleDOI
Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talk
TL;DR: This paper focuses onto dynamically reconfigurable logic (DRL) LSI, a prototype chip that was developed to evaluate the reconfigured computing concept and can accelerate media/communication applications with customized hardware configurations, yet maintaining scalability towards varying application sizes.
References
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Proceedings ArticleDOI
Garp: a MIPS processor with a reconfigurable coprocessor
Jay Hauser,John Wawrzynek +1 more
TL;DR: Novel aspects of the Garp Architecture are presented, as well as a prototype software environment and preliminary performance results, which suggest that a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factors of 24 for some useful applications.
Proceedings ArticleDOI
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Rahul Razdan,Michael D. Smith +1 more
TL;DR: A novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications through a coupling of compile-time analysis routines and hardware synthesis tools is explored.
Proceedings Article
MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources
Ethan Mirsky,AndrC DeHon +1 more
TL;DR: MATRIX as discussed by the authors is a coarse-grained, reconfigurable com- puting architecture which supports confgurable instruction distribution, where device resources are allocated to control- ling and describing the computation on a per task basis.
Dissertation
Reconfigurable Architectures for General-Purpose Computing
André DeHon,Thomas F. Knight +1 more
TL;DR: MATRIX is developed, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs, and it is shown that MATRIX yields 10-20$\times the computational density of conventional processors.
Proceedings ArticleDOI
MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources
TL;DR: MATRIX is a novel, coarse-grain, reconfigurable computing architecture which supports configurable instruction distribution that can serve as an instruction store, a memory element, or a computational element, and the adaptability is made possible by a multi-level configuration scheme.