Proceedings ArticleDOI
Universal test complexity of field-programmable gate arrays
TLDR
This paper proposes a programming scheme called block-sliced loading, which makes FPGAs C-testable, and presents two types of programming schemes; sequential loading and random access loading.Abstract:
A field-programmable gate array (FPGA) can implement arbitrary logic circuits in the field. In this paper we consider universal test such that when applied to an unprogrammed FPGA, it ensures that all the corresponding programmed logic circuits on the FPGA are fault-free. We focus on testing for look-up tables in FPGAs, and present two types of programming schemes; sequential loading and random access loading. Then we show test procedures for the FPGAs with these programming schemes and their test complexities. In order to make the test complexity for FPGAs independent of the array size of the FPGAs, we propose a programming scheme called block-sliced loading, which makes FPGAs C-testable.read more
Citations
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Journal ArticleDOI
Testing the interconnect of RAM-based FPGAs
TL;DR: The authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.
Proceedings ArticleDOI
Test of RAM-based FPGA: methodology and application to the interconnect
TL;DR: A methodology for testing RAM-based FPGA taking into account the configurability of such flexible devices is proposed and it is demonstrated that a set of only 3 Test Configurations suffice to make 100% of the considered realistic fault set non-redundant.
Proceedings ArticleDOI
A test methodology for interconnect structures of LUT-based FPGAs
TL;DR: This paper heuristically derive test procedures for the faults of programmable interconnect structures of look-up table based FPGAs and shows their validness and complexity.
Journal ArticleDOI
On-line fault detection for bus-based field programmable gate arrays
TL;DR: A technique for on-line built-in self-testing of bus-based field programmable gate arrays (FPGAs) without using special-purpose hardware, hardware external to the device, and without interrupting system operation is introduced.
Journal ArticleDOI
Universal fault diagnosis for lookup table FPGAs
TL;DR: Focusing on configurable logic blocks in a lookup table FPGA, the authors present universal fault diagnosis procedures that can locate a fault to just one CLB.
References
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BookDOI
Field-Programmable Gate Array Technology
TL;DR: The purpose of this chapter was to discuss the design and implementation of SRAM Programmable FPGAs, as well as some of the techniques used in the development of Erasable Programmable Logic Devices.
Journal ArticleDOI
Easily Testable Iterative Systems
TL;DR: Property of systems that enable them to be tested with a fixed constant number of tests independent of p, the number of cells in the system are considered, referred to as C-testable.
Journal ArticleDOI
Functional Testing of Semiconductor Random Access Memories
TL;DR: An overview of the problem of testing semiconductor random access memories (RAMs) and several fault models, including the stuck-at-0/1 faults, coupled-cell faults, and single-cell pattern-sensitive faults are presented.
Book ChapterDOI
Fault Modeling and Test Generation for FPGAs
TL;DR: A fault model for one-time programmable FPGAs is derived from the general functional fault model and an algorithm to perform test generation according to this model and a fault coverage of 100% can be achieved regardless of the final implementation of the circuit.
Book ChapterDOI
A Test Methodology Applied to Cellular Logic Programmable Gate Arrays
TL;DR: This paper describes an approach for testing a class of programmable logic devices called Cellular Programmable Gate Arrays, which provides a reduced number of reprogramming times during test mode and a possibility of testing more devices in a defined period of time.