Showing papers on "Adder published in 1975"

Parallel digital arithmetic device having a variable number of independent arithmetic zones of variable width and location

Abstract: A carry look-ahead parallel digital adder having a relatively wide overall data flow width and a pair of automatically adjustable boundary mechanisms for subdividing the adder into plural independent operating zones of variable width and variable location. Anywhere from one to three independent zones may be obtained. Independent external carry-in and carry-out lines are provided for each zone and the connecting points for such lines are automatically shifted in step with the movement of the zone boundaries.

Feedback residue compression for digital speech systems

Abstract: A digital speech compression system uses a predictive feedback loop. The digital speech signals are compressed within the feedback loop for reducing the transmitter bandwidth. The system comprises a first adder into which the digital signal is fed followed by a quantizer and a compression logic. The predictive loop includes a second adder coupled to the compression logic and followed by a digital predictive filter. The output of the filter is impressed in a negative sense on the first adder and in a positive sense on the second adder. Specifically, the quantizer and compression logic may consist of a two-valued limiter followed by a compressor and a converter in the feedback loop or alternatively the limiter may be followed by a converter while the compressor is disposed outside the feedback loop to provide sample by sample compression.

Electronic cash register

Abstract: An electronic cash register comprising: a power source for energization of said electronic cash register, a power recovery detecting circuit operatively coupled to said power source for detecting the power recovery after occurrence of the power failure, a keyboard for entering numerals and various functions, first price and department code registers for storing the entered price and department code of commodities, respectively, a counter for counting the number of digits of the department code, an adder responsive to the count up output of the counter for providing a cumulative total amount of the prices of the commodities, a total amount non-volatile register for storing the cumulative total amount, a second price and department code non-volatile registers responsive to the count up output of the counter for receiving and storing the price and department code information stored in the first price and department registers respectively, and a printing means responsive to the total, the second price and the second department code registers for printing out the total, price, and department code of the commodities, said printing means being adapted to be responsive to said power recovery detecting circuit for printing out again the datas which were to be printed out before the occurrence of power failure

Digital polynomial function generator

Abstract: Apparatus for obtaining a numerical value of a polynomial function of a variable. The method of cascade accumulation is used in which memories M0, M1, M2, . . . , Mn are involved, and under one cycle of manipulation, the content of memory M1 is added to the content of M0, the content of M2 is added to the content of M1, and so on until the content of Mn is added to the content of Mn-1. By loading a digital value determined by the coefficients of the polynomial a 0 , a 1 , a 2 , . . . , a n in each of the memories as its initial value, and repeating x cycles of the above mentioned manipulations, the digital value of the function w = a.sub.0 + a.sub.1 x + a.sub.2 x.sup.2 + . . . + a.sub.n x.sup.n is obtained in the memory M0. A simplified electrical circuit for performing the above manipulation is disclosed, in one example of which only memories or a shift register and an adder are involved as key elements in the logic circuit to generate a polynomial function, and no complicated programming is needed.

High speed parallel digital adder employing conditional and look-ahead approaches

Abstract: A high speed parallel digital adder/subtracter employing a specially chosen combination of "conditional" and "look-ahead" approaches which permits economically achieving high speed operation even for input operands containing relatively large numbers of digits. In a preferred embodiment, simultaneously produced look-ahead carry and carry-not signals are generated and employed to select particular ones of simultaneously generated conditional sums for one or more operand digits so as to simultaneously provide resulting digital sums which properly represent the sum of the input operands.

An experimental multiplier circuit based on superconducting Josephson devices

Abstract: This paper describes the design, testing, and operation of a 4-bit multiplier circuit based on Josephson tunneling logic (JTL) gates. The algorithm adopted was that of a simple serial 4-bit multiplier consisting of a 4-bit adder with ripple carry, together with a four phase, 8-bit accumulator shift register. The circuit, fabricated using a 25-/spl mu/m minimum linewidth technology, operated with a minimum cycle time of 6.67 ns (a limit imposed by the external test equipment) giving a 4-bit multiplication time of 27 ns with an average power dissipation of 35 /spl mu/W per logic gate. With better external pulse generators, or internal Josephson junction generators, the present circuit has been simulated to operate with a 3.0-ns cycle giving a 4-bit multiplication time of 12 ns.

Digital beamforming system

Abstract: Each ring of a two ring transducer array provides signals that are bandpad filtered and hard-clipped. These signals are sampled in parallel at a predetermined frequency. The sampled signals are conducted to Adder circuits with appropriate delays being applied to predetermined signals. By sequentially changing the signals having a delay inserted and those applied directly to the Adder a 360° azimuthal scan is provided in discrete angular steps. The sums of Adders of each ring are then combined. The system provides scans in the horizontal direction and at predetermined depression/elevation angles.

Arithmetic Networks and Their Minimization Using a New Line of Elementary Units

Abstract: A family of switching networks, called "arithmetic networks," is investigated. The elementary units of these networks are generalizations of full adders that can process input signals of different weights.

High speed binary multiplication system employing a plurality of multiple generator circuits

Abstract: A multiplication apparatus comprises a plurality of multiple generator circuits, each of which simultaneously generates binary signals representative of a predetermined multiple of a multiplicand for different digits of a group of multiplier digits. A different one of the multiple generator circuits couples to a different one of a plurality of serially connected adder circuits for applying the binary signals. Each of the multiple generator circuits includes storage circuits coupled to receive timing signals from a common source to enable an overlap in the generation of binary multiple signals minimizing the number of multiplication cycles required to perform a multiplication operation in response to multiply instructions.

Frame-to-frame coding system

Abstract: An input video signal is fed to a substracter wherein a difference is taken between the input and the output from a frame memory to provide a difference signal, the magnitude of which is controlled by a magnitude adjuster. The controlled output is then fed to a threshold circuit, from which a significant difference signal is derived which has a magnitude above a given level. The significant difference signal is quantized by an encoder into a code having a reduced number of bits as compared with the inputted significant difference signal. The quantized code is written into a buffer memory, and is read out therefrom at a uniform bit rate to a transmission line. A sum of a signal indicative of the representative level of the quantized code from the encoder and the output of the frame memory is formed in an adder, and the sum signal is written into the frame memory and read out subsequently or after one frame. The occupancy of the buffer memory is detected to provide a control over the magnitude adjuster in accordance with the detected value so as to prevent an overflow from the buffer memory. A signal to refresh the frame memory located on the receiving side is transmitted by writing the output of the adder into the buffer memory after switching from the output of the encoder to the output of the adder.

Adder with fast detection of sum equal to zeroes or radix minus one

Abstract: Logic circuits in an adder for use in data processing for the detection of a sum of all ZEROES together with the mathematics upon which the circuits are based. Circuits and mathematics are also disclosed for a detection of a sum of all digits equal to the radix less one. Each of these detected sum conditions are produced prior to or at least concurrently with the production of the sum itself.

Arithmetic unit for a digital data processor

Abstract: A digital arithmetic unit for adding and subtracting multidigit binary coded decimal numbers having a zoned format. Such adding and subtracting is done by means of a parallel binary adder of a type suitable for handling pure binary numbers and having no special provisions for accommodating zoned decimal numbers. The two multidigit zoned decimal numbers to be added or subtracted at any given moment are supplied to the two input sides of such binary adder by way of input modifier circuits which precondition the zone and sign fields in such numbers to enable the proper propagation of digit carries across such zone and sign fields during the performance of the addition inside the binary adder. The resulting binary bit sequence appearing at the output side of the binary adder is passed to an output modifier or corrector which causes the bits in the zone and sign field positions therein to assume the proper zone and sign code values. The input modifier circuitry for one of the numbers also includes circuitry for increasing the value of each digit in such number by a factor of six for enabling the proper generation of digit carries inside the binary adder. The output corrector includes circuitry for reducing, when necessary, the value of one or more of the output digits by a factor of six to offset the increase in the input digits. Subtraction is accomplished by complementing one of the numbers before it is supplied to the binary adder. Sign handling circuitry detects the polarities or signs of the two input numbers as well as the status of an external add/subtract command and processes these three factors to develop a control signal for controlling the use of the complementing action for enabling the number appearing at the output of the output corrector to be in true magnitude form whenever possible. The input modifier circuitry, the output corrector and the sign handling circuitry are constructed so that packed binary coded decimal numbers and pure binary numbers can also be handled by the arithmetic unit.

Digital equalizer for data-transmission system

Abstract: Incoming data pulses from a transmission channel are differentially combined with feedback pulses from the downstream end of a cascade of (N-1) delay networks to form an updating signal fed in parallel to a first set of multipliers for weighting with respective coefficients b 1 - b N -1 . These multipliers deliver optimized signal components to the inputs of respective delay networks of the cascade, through the intermediary of adders in each instance except for the first delay network at the upstream end; a further adder downstream of the last delay network may superimpose the updating signal, weighted with a coefficient b N by an N th multiplier of the first set, upon the feedback pulse issuing from the last delay network to generate an additional signal component. At least the more significant signal components, from the inputs of the delay networks located further upstream in the cascade, are weighted in a second set of multipliers with respective coefficients a 1 , a 2 etc. before being additively combined, in a summing circuit, into a composite output signal.

Fast multiplier circuit employing shift circuitry responsive to two binary numbers the sum of which approximately equals the mantissa of the multiplier

Abstract: A multiplier for multiplying a fixed point multiplicand by a floating point multiplier utilizes decode logic which provides control signals related to two numbers, the sum of which is approximately equal to the mantissa of the multiplier. The multiplicand is separately left shifted in two circuits, responsive to the control signals, by a number of places respectively corresponding to the values of said two numbers. The shift circuit outputs are summed algebraically in an adder. The sum is then shifted by a number of places and in a direction determined respectively by the magnitude and sign of the power of the floating point multiplier. The result is a close approximation of the desired multiplication product. The multiplier advantageously is employed in an electronic musical instrument.

Arithmetic unit for use in a digital data processor and having an improved system for parity check bit generation and error detection

Abstract: A digital arithmetic unit employing a binary adder for adding and subtracting multidigit binary coded decimal numbers in either zoned format or packed format and having an improved method of generating parity check bits for the resultant data bytes produced by the arithmetic unit. When using a binary adder for adding or subtracting binary coded decimal numbers, it is necessary to correct some of the data appearing at the output of the binary adder in order to obtain the correct results. The parity check bit generating circuitry of the present invention, however, works on the uncorrected data appearing at the output of the adder, but nevertheless produces the proper parity check bits for the corrected data which represents the final output for the arithmetic unit. This reduces the amount of time delay which would otherwise be caused by generating the parity check bits in a conventional manner.

High-speed adder

Abstract: A high-speed adder circuit capable of performing addition with binary nums in 1's complement, 2's complement or sign-magnitude formats. The adder can be made in the form of a single chip that can be assembled in multiple units to expand its capacity. There is a provision for converting minus zero to plus zero so as to prevent oscillations from occurring in the loop circuit. Also, the sum output is automatically shifted to the correct format when an overflow condition occurs.

One-error correction convolutional coding system

Abstract: A rate one-half random error convolutional coding system corrects the theoretical limit of one error out of four successive bits An information bit stream is processed through the system encoder which is comprised of a two-bit shift register and a modulo-2 adder The encoder generates a parity bit formed by the modulo-2 summing of successive pairs of information bits, and produces a convolved transmission bit stream The system decoder is the replica of the encoder in combination with a two-bit syndrome register, an AND gate, complementary feedback circuitry, and an output modulo-2 adder Overall system performance is the simplest, fastest, and highest performing of all such systems known to date

High-speed m sequence generation: a further note

Abstract: A method of generating maximal-length sequences by employing delay lines in place of shift-register elements is described. Speed of operation is limited only by the rise and fall times of the modulo-2 adder employed.

Integrated circuit microprocessor with parallel binary adder having on-the-fly correction to provide decimal results

Abstract: Disclosed is an integrated circuit microprocessor with a parallel binary adder whose output can be corrected on-the-fly to provide decimal results. The correction is by logical gating which operates selectively and on-the-fly, that is, while the sum from the output of the binary adder is being transferred to an accumulator. As a result, the same binary adder can provide the binary sum of the operands supplied to it, or the binary coded decimal sum of bcd operands, or the binary coded decimal difference of bcd operands, in a single operating cycle and without the need to recycle the sum of the operands through the adder. This single cycle correction significantly speeds up the operation of the invented microprocessor as compared to known prior art microprocessors which recycle the adder output when a binary coded decimal sum or difference is required.

Digital electronic watch

Abstract: PURPOSE: To provide an adder to digital electronic watch and subsequently increase known time differences, thereby letting the time corresponding to each local time be displayed by an access mode. COPYRIGHT: (C)1977,JPO&Japio

Carrier wave reproducer device for use in the reception of a multi-phase phase-modulated wave

Abstract: A carrier wave reproducer device for use in the reception of a multi-phase digital phase-modulated waves for rapidly extracting the carrier wave without the generation of frequencies higher than the carrier frequency is disclosed. In its simplest embodiment, the device employs a delay detector and a cumulative adder circuit to derive a demodulated signal and a modulator for inversely modulating the input multi-phase digital phase-modulated wave with said demodulated signal. The reference carrier wave is then obtained from the output of the modulator. The same principle is used in alternative embodiments used in the reception of a burst form of signal transmitted with a preamble word having a specific pattern. These alternative embodiments take advantage of the preamble word generally included in a burst form of signal by additionally employing a demodulator for demodulating the input multi-phase digital phase-modulated wave through synchronized detection by making use of the reference carrier wave obtained from the modulator. In addition, a switching circuit is employed to supply the modulator with the demodulated output from the adder circuit at the beginning of reception of the phase-modulated wave, but after the reference carrier wave has been established, to supply the modulator with the output of the demodulator.

Digital function generator

Abstract: Digital function generator apparatus providing an output Y from an input X according to ##EQU1## Included in the apparatus is a digital memory, a digital adder, a digital multiplier, and also timing control means.

Video image positioning control system

Abstract: For controlling the direction and rate of movement of an image on a raster scan display, a first set of counters is arranged to generate digital pulses for use as horizontal and vertical sync pulses for use in conjunction with a video adder for controlling the image on the display. Means, such as a second set of counters, driven by another clock means, provides an output which is compared to that of the first named counters to provide information signals to the video adder for controlling the location and movements for the image being displayed.

Binary parallel computing arrangement for additions or subtractions

Abstract: A parallel adder with sequential carry ripple is subdivided into sections. Detector circuits are distributed over the various digit positions of the adder. Each detector circuit receives the digit pairs of the input operands of at least one adder position. The detection circuits indicate the beginning or the end of a carry ripple chain by testing the condition "both input digits zero or both input digits one". Via a coder, the output signals of the detection circuits are combined in the form of group indicating signals, each of which corresponds to a predetermined distance between the digit positions. By means of the group indicating signals a clock circuit is controlled in such a manner that the operating time is limited to the time required for carry rippling.

Equalizer for partial response signals

Abstract: An equalizer for correcting distorted, received data signals, i.e., partial-response signals, is described. The equalizer is of the type which uses a multi-stage shift register and an analog adder, the latter of which emits the corrected signal. In the transmission path between the output of the analog adder and the first stage of the shift register a second analog adder is interposed. An output of one of the succeeding stages of the shift register is connected directly to a second input of the second analog adder. The output of the second analog adder is coupled either directly or indirectly to the first stage of the shift register.

Addition control system

Abstract: A system for controlling the addition of signed binary numbers represented with N bits, of the 2's complement notation, is disclosed which includes addend and augend sign control circuits, and an adder circuit comprising a carry save adder and a carry proper gate adder. The addend sign control circuit receives an operation command sign signal (B, --B, |B| or --|B|) for the addend, which designates the addend of the certain type (B, |B| or --|--B|) to be applied directly to the carry save adder and designates the addend of another type (--B, |--B| or --|B|) to be applied to the carry save adder through a 1's complementer. The augend sign control circuit functions similarly for the augend being applied to the carry save adder. A corrective number (0, 1 or 2) is applied to the adder circuit which corresponds to neither, one, or both the addend and augend being applied to the adder circuit through their respective 1's complementer.

Picosecond Gunn-effect carry generator for binary adders

Abstract: A four-bit carry generator for high speed logic, fabricated with GaAs in integrated circuitry, will be described. Utilizing lateral spreading of a Gunn domain, a four-bit carry propagation delay of 50 ps has been obtained.

On Overflow Detection and Correction in Digital Filters

Abstract: A new method for correction of two's, complement adders characteristics at the output of the multiplier following the adders is proposed. It is very suitable to ordinary pipe-line implementation.

Electro mechanical adder mechanism

Abstract: An adder mechanism with a plurality of adder links, each of which contains a thick section and a thin section, each adder link may have a selected section placed in a effective position by a plurality of link actuators individually connected to the adder links. Adder spacers interconnect the adder links at the effective position whereby the total dimension of the adder spacers and the selected thin or thick sections in the effective position may be utilized to influence, for example, stitch forming instrumentalities of a sewing machine. The adder mechanism is supported in a frame which also supports a drive shaft. A plurality of collars, one for each link actuator, is slidably keyed to the drive shaft to rotate therewith. Each collar is formed with at least one tooth, designed to engage with one or the other of a pair of oppositely disposed and axially spaced apart teeth on an internal surface of the link actuator thereby to drive the link actuator and connected adder link with its thin section or its thick section to the effective position adjacent the adder spacer. A solenoid is utilized to alter the position of the collar that a selected one of the spaced apart teeth on the link actuator may be engaged.

Binary full adder circuit

Abstract: PURPOSE:To design a higher speed operation of a binary full adder by transmitting a carry through signal through complementary MOS transmitting gates.