Showing papers on "Adder published in 1979"

Processing element for parallel array processors

Abstract: A processing element constituting the basic building block of a massively-parallel processor. Fundamentally, the processing element includes an arithmetic sub-unit comprising registers for operands, a sum-bit register, a carry-bit register, a shift register of selectively variable length, and a full adder. A logic network is included with each processing element for performing the basic Boolean logic functions between two bits of data. There is also included a multiplexer for intercommunicating with neighboring processing elements and a register for receiving data from and transferring data to neighboring processing elements. Each such processing element includes its own random access memory which communicates with the arithmetic sub-unit and the logic network of the processing element.

Optical residue arithmetic: a correlation approach

Abstract: A numerical optical processor is described that performs operations in residue arithmetic. The position coding used to represent decimal and residue numbers allows one to describe the various conversions and operations in a correlation formulation. This description of residue arithmetic leads directly to novel residue adder and decimal/residue/decimal converter designs, which are described and experimentally demonstrated. The accuracy, dynamic range and space bandwidth of an optical residue arithmetic processor are also discussed.

Iterative color-multiplexed, electro-optical processor

Abstract: A noncoherent optical vector-matrix multiplier using a linear LED source array and a linear P-I-N photodiode detector array has been combined with a 1-D adder in a feedback loop. The resultant iterative optical processor and its use in solving simultaneous linear equations are described. Operation on complex data is provided by a novel color-multiplexing system.

An 0(n) Parallel Multiplier with Bit-Sequential Input and Output

Abstract: Previous proposals for fast multipliers are discussed, along with a summary of the known theoretical limitations of such designs. Then, a new parallel multiplier with a very simple configuration is suggested. This multiplier operates in time 0(n), where n is the maximum of the lengths of the multiplier and multiplicand, both of which are fixed point, expressed in binary notation. It is a logical circuit consisting of 2n modules, each being only slightly more complex than a full adder; instead of three inputs and two outputs, each module has five inputs and three outputs. A logical circuit realization is given for the modules. But perhaps the most significant aspect of this design is the property that the input is required only bit-sequentially and the output is generated bit-sequentially, both at the rate of one bit per time step, least significant bit first. The advantages of such bit-sequential input and output arithmetic units are described.

Development Of An Optical Parallel Logic Device And A Half-Adder Circuit For Digital Optical Processing

Abstract: An Optical Parallel Logic (OPAL) device which performs Boolean algebraic operations on two binary images has been developed. This device consists of a photoconductor and an electro-optic light modulating material appropriately arranged to bring about an in-teraction between the input signals. Two such OPAL devices have been interconnected to form a half-adder circuit (one of the essential components in the CPU of a futuristic digital optical processor). Operation of an 8 x 8 OPAL device containing CdS (photoconductor) and twisted nematic liquid crystal (electro-optic light modulating material) is reported. A contrast ratio of 20:1 was obtained. A circuit composed of two such devices is shown to perform addition of two 8 x 8 binary images generating SUM and CARRY images.

High-speed programmable logic array adders

Abstract: Programmable Logic Array (PLA) adders are described which perform an addition in one cycle with a single pass through a PLA and require a reasonable number of product terms for an 8-, 16-, or even a 32-bit adder. The PLA features two-bit input decoders feeding an AND array followed by an OR array whose outputs are pairwise Exclusive-ORed. Carry-look-ahead adder equations, adapted to the PLA to require relatively few product terms, are adjusted for maximum sharing of product terms. The number of unique product terms is a relative measure of one of the physical dimensions of the PLA. Equations for contiguous sum bits are grouped into strings, each using a common input carry. A procedure optimally assigns sum bits to strings to further minimize the total number of unique product terms. The methods are extended to PLAs with decoders of increased inputs and substantially reduced product terms. They can serve as dedicated macro functions on a chip, using special decoders relevant to adders. As a result, the other PLA dimension comprising the number of outputs from all input decoders increases only moderately, and can even decrease, with larger decoders. Finally, the PLA adder can be further substantially compressed by splitting the OR array into two parts such that a row of the AND array is shared between two product terms, and an OR array column is shared between two sums of product terms.

High speed multiplier using carry-save/propagate pipeline with sparse carries

Abstract: A high speed multiply apparatus minimizes latch requirements and I/O pin requirement between chips by a new configuration which iteratively adds four multiples of a multiplicand in a stage of 4-2 carry save adders which then feed four-bit parallel adders each having four sum outputs and a carry output from the highest order bit position. Only the sum outputs are latched and then fed to a carry propagate adder on each iteration for addition to the previous partial products. Only the single carry output from each of the 4-bit parallel adders needs to be latched and then fed to another 4-bit parallel adder.

Measuring device for transmitting measuring signals via an optical link

Abstract: A measuring device has a transmitter side that is connected to a receiver side over an optical transmission link. The transmitter side receives an input measurement signal from a transducer and applies the input signal to an adder that also receives a feedback signal from the receiver side. The adder generates a comparison signal that corresponds to the difference between the input signal and the feedback signal. The comparison signal is applied to a regulator on the receiver side. The regulator generates the feedback signal and an output signal having a magnitude corresponding to the magnitude of the input signal. Amplification of the feedback signal on the receiver side is controlled by time division or frequency division calibration signals, so that the total amplification of the feedback signal between the adder and the regulator is held constant.

High-speed digital bus-organized multiplier/divider system

Abstract: A bus organized 16×16 (or 8×8) high-speed digital bus-organized multiplier/divider for high-speed, low-power operation is implemented on a single semiconductor chip. Four working registers each of 16 (or 8) bits are used in the system. These registers are a multiplier register, a multiplicand and divisor register, a first accumulator register for storing the least significant half of a double length product after a multiplication of the remainder after a division operation, and a second accumulator register which stores the most significant half of the product after a multiplication or the quotient after a division operation. A decoder is connected to the multiplicand and multiplier registers to implement the Modified Booth Algorithm and to encode the 16 (or 8) multiplier digits. The system operates to shift the multiplier number through the multiplier register to a position where the Modified Booth Algorithm encoding takes place. The Modified Booth encoder then controls the operation of multiplexer circuits to which the outputs of the multiplicand register are applied to produce successive partial products. A carry/save arithmetic logic unit operates in conjunction with the registers to cause accumulation and storage of multiplication products and division quotient/remainders in the double length accumulator registers which provide a 32 bit output number. BACKGROUND OF THE INVENTION High speed digital multipliers and digital dividers have a wide number of applications in digital signal processing. Multiplication or division of binary numbers can be performed in a relatively simply manner. For multiplication, a classic approach is to provide an accumulate register which has twice the length n of the operands, because the product can approach twice the size of the operands. The multiplier is conveniently stored in the less significant half of the accumulator register. The most significant half and the contents of a multiplicand register are applied to an adder. The output of the adder is effectively the sum of the accumulated partial products and the potential partial product consisting of one times the multiplicand. A series of n cycles is set up. For each cycle, the least significant bit of the accumulator is examined; and the output of the adder is stored in the more significant half of the accumulator or not, in accordance with that bit being a binary "1" or a "0", respectively. The accumulator then is shifted to the right one bit, and the cycle is repeated until the entire multiplier has been examined. As a consequence, the multiplicand has been multiplied by 2n, for every "1" bit in the multiplier; and these partial products have been accumulated with the proper alignment due to the cyclic shifts which divide the result by 2 in each cycle. Various techniques exist in the art for handling different sign combinations of the operands, for the different types of number representations, that is, sign and magnitude, 1's complement and 2's complement. A problem which exists with a digital multiplier of the type just described is that for 16 bit operands, the process calls for 16 cycles to obtain each of the 16 different partial products. These partial products then are added together in an additional 16 adder circuits to obtain the final resultant product, and all of the gates and other circuitry results in dissipation of a substantial amount of power. In addition, as the size of the multiplier increases (for example from an 8×8 to a 16×16 or a 32×32 multiplier), the length of time for accomplishing the multiplication increases in direct proportion. Because of the large number of circuit components which are necessary with such a prior art approach, implementation of large multipliers on a single LSI chip has not proved practical. As a result such circuitry is usually implemented in several chips which must be interconnected together externally to form the complete circuit. Another disadvantage with the standard prior art approaches is the dissipation of relatively large amounts of power, so that it is necessary to employ forced air cooling or other types of cooling during the operation of the system. The resultant machine is correspondingly increased in complexity and cost as a result of the relatively high power dissipation. A solution to some of the problems inherent in the prior art is disclosed in U.S. Pat. No. 4,153,938 issued May 8, 1979 filed on Aug. 18, 1977 and assigned to the same assignee as the present application. In this copending application, a high speed 8×8 digital multiplier is implemented in a single LSI chip using circuitry for implementing a Modified Booth Algorithm to examine the binary multiplier 3 bits at a time and shifted 2 bits at a time in sequence for performing the multiplication function. In the copending application, this examination is effected through the use of several Modified Booth encoder gating circuits, each responsive to a different group of 3 bits of the multiplier input register, for controlling the shifting of the outputs of the multiplicand register applied to the input of an array of carry/save adder circuits to effect the desired multiplication. The result is a reduction in the number of cycles required to complete the multiplication operation and a reduction in the circuitry necessary to carry it out, along with reduced power dissipation. It is desirable to implement a 16×16 multiplier on a single integrated circuit chip and further to implement a 16×16 multiplier/divider system on a single IC chip for high speed operation with minimal power consumption. Other features which are desirable in such multiplier/divider circuits, and which are particularly desirable in circuits implemented in a single integrated circuit chip, are the ability to multiply and accumulate in a single cycle of operation, to perform the entry of new data from the input busses simultaneously with the processing of previous entries, and the multiplication or division of new entries or accumulated entries by a constant. SUMMARY OF THE INVENTION It is an object of this invention to provide an improved high-speed digital multiplier. It is another object of this invention to provide an improved high-speed digital multiplier/divider. It is an additional object of this invention to provide a high-speed digital multiplier of at least 16 bits by 16 bits on a single semiconductor chip. It is still another object of the invention to provide a high-speed digital multiplier/divider on a single semiconductor chip having reduced power dissipation. It is still a further object of this invention to provide a bus organized multiplier/divider having a variety of different multiply and divide options controlled by external instruction signals. Yet another object of this invention is to implement a high-speed, low-power dissipation digital multiplier/divider system utilizing circuitry which generates a reduced number of partial products. In accordance with the preferred embodiment of this invention, a digital multiplier circuit includes registers for receiving the multiplier inputs and the multiplicand inputs. A partial product generator coupled to the registers includes an encoder which encodes the multiplier inputs according to the Modified Booth Algorithm to produce control signals which are applied to a plurality of multiplexer circuits interconnecting the multiplicand register with the partial product generating circuitry to produce the resultant number. The information in the multiplier register is shifted on a step-by-step basis through the register to present the contents of the register to the encoder circuitry; so that only a single Modified Booth Algorithm encoder circuit is required, irrespective of the length of the multiplier in the multiplier register. In more specific embodiments of the invention, accumulator registers are provided and the system includes operating mode control circuitry for permitting operation of the system either as a multiplier or as a divider. In addition, a state counter is used in conjunction with external mode control signals applied to the circuit to permit a variety of multiplication and accumulation functions as well as a variety of divider functions to be accomplished by the system. These functions include positive and negative multiplication, positive and negative accumulation, multiplication by a constant, and both single and double length addition in conjunction with mmultiplication, along with divide options including single or double length division, division of a previous generated number, division by a constant, and continual division of a remainder or quotient.

Adaptive filter with tap coefficient leakage

Abstract: Adaptive filters are commonly used in echo cancelers and automatic equalizers. Usually adaptive filters include a tapped delay line and apparatus coupled to the delay line for producing a tap coefficient signal, whose sign and magnitude indicate the appropriate correction in adjusting the filter. However, in the presence of input signals having a partial frequency band spectrum, known filters tend to become unstable, e.g., tap coefficient signals blow up. The instant arrangement includes apparatus for weakly driving the tap coefficient signals to optimal values. As illustrated in a deceptively simple embodiment, a tap coefficient updating component is extended through a one's complement converter to a first input of a binary adder. A two's complement output of the adder is fed back to a second input of the adder. The sign of the adder output is also provided to a CARRY-IN input terminal of the adder. Functionally, a unit leak is introduced in the least significant bit of the adder output tap coefficient signal whenever the updating component and the tap coefficient signal are of opposite algebraic signs. Otherwise, no leak is introduced. Thereby the tap coefficient signal is weakly driven toward zero.

Integrated optical half adder circuit

Abstract: An integrated optical half adder circuit was fabricated on LiNbO3 substrate. The circuit is composed of several elementary logic gates. Interaction between guided light beams was achieved by utilizing LiNbO3 electrooptic modulators, which operate by changing the cutoff condition of the lowest order guided mode in an outdiffused LiNbO3 channel waveguide, and CdS photodetectors. Light signals were injected into an array of channel waveguides by end-fire coupling from an array of four single mode optical fibers arranged in preferentially etched V-grooves in silicon.

Monitor system for a digital signal

Abstract: A monitor system comprising: an adder for summing up a plurality of unknown analog electric quantity signals denoting the operating conditions of such as a transmission line; a multiplexer for generating output signals corresponding to the plural analog electric quantity signals and also to a signal denoting the result of addition made by said adder; an A-D converter for converting output analog signals from the multiplexer into digital signals; and a monitor which sums up those of the output digital signals from the A-D converter which correspond to said plural analog electric quantity signals, compares a signal denoting the result of said addition with a digital signal converted from an output signal from the adder, receives an error detection signal denoting the known prescribed electric quantity converted into a digital signal through the multiplexer and A-D converter, and judges the operating condition of the A-D converter from the contents of said received digital signal.

Complex ternary correlator and method for adaptive gradient computation

Abstract: A complex ternary correlator and method for adaptive gradient computation in an adaptive equalizer and including four ternary operation circuits, four ternary multiplier circuits for obtaining the cross products of the ternary operation outputs, a subtractor circuit for developing a signal commensurate with the difference between two of the ternary multiplier outputs, an adder circuit for developing a signal commensurate with the sum of the remaining two ternary multiplier outputs and two identical integrating circuits for obtaining the real and imaginary adaptive tap coefficient update increments in an adaptive equalizer.

Video signal recording and reproducing device

Abstract: PURPOSE:To improve color reproduction in special reproduction by performing the angle modulation of a luminance signal and the low frequency conversion of a chrominance signal and also by recording signals so that a shift of the horizontal synchronizing signal on the adjacent track will be a multiple of one horizontal synchronizing signal interval. CONSTITUTION:A reproduced signal obtained from reproducing head 7 is extracted from a luminance signal through high-pass filter 8 and frequency demodulator 10. A color signal is restored to an original chrominance signal through low-pass filter 9 and frequency converter 11. This restored chrominance signal is applied to adder 12 as it is in normal reproduction. In special reproduction for slow motion, still pictures, etc., it is applied to adder 12 by way of 1H delay line 14. The reproduced signal from head 7 is also applied to flip-flop 20 by way of envelope detector 16, pulse generator 17, integrating circuit 18, and inhibiting circuit 19 and used there as a switching signal for change-over unit 21 to apply adder 12 with a 1H delay signal in the special reproduction. Consequently, the deterioration of reproduced- picture quality accompanying track switching is prevented.

Cutting control apparatus

Abstract: A cutting control apparatus for cutting, by a rotary type flying cutter, a sheet, pipe or like material fed by a feeder. On the basis of a synchronous cutting length corresponding to setting of a blade speed change mechanism of the flying cutter and one of a travelling speed signal of the material and the revolving speed of a blade of the cutter, a reference speed signal is produced for the other of the material travelling speed and the blade revolving speed. One of a signal related to length-measuring pulses corresponding to the distance of travel of the material and a signal related to rotation pulses corresponding to the rotation of the blade is applied as an additive input to an adder, and the other is applied as a subtractive input to the adder. The adder is supplied, for each cutting, with a correction value calculated by an arithmetic circuit on the basis of a set cutting length and the synchronous cutting length, and the output from the adder is converted into an analog signal, which is used as a correction signal for the reference speed signal.

Absolute difference generator for use in display systems

Abstract: An absolute difference generator comprises an adder, an Exclusive-OR, two inverters and a latch. One input number is inverted, then presented to one input of the adder while the other input number is presented to the other input of the adder. The carry out line of the adder sets a latch, the output of which is fed back to the carry in line of the adder. The latch output is also combined with the adder output in an Exclusive-OR to control inversion of the adder output and produce the absolute difference between the input data.

Autocalibration of compressed A/D converter

Abstract: An analog-to-digital converter system is disclosed in which the amplitude of the signal is compressed by means including a logging means prior to an analog-to-digital converter. Reference signals of known values are applied to the logging means and their values at the output of the converter are used to determine a linearity factor which is applied to a multiplier coupled to the output of the converter. The amplitude of one of the reference signals at the output of the multiplier is compared with what it should be and the difference is added by an adder at the output of the multiplier.

Optical focusing device

Abstract: An optical information system is provided with an optical focussing device for adjusting a position of an objective lens. The optical focussing device is comprised of a photosensing unit to which a part of a light beam reflected from a disc and passed through the objective lens is projected through a semitransparent mirror and a cylindrical lens. The photosensing unit for detecting a shape of the projected image of the light beam is assembled by a first photo-cell having a narrow photoelectric surface extending in the direction of movement of the projected image and second and third photo-cells each having a rectangular photoelectric surface closely disposed to the first photo-cell surface. The second and third photo-cells are connected to a adder to sum signals detected by both cells. The adder and the first photo-cells connected to a differential amplifier to compare the signal detected by the first photo-cell with the output of the adder. The differential amplifier is connected to a objective lens moving unit to supply a lens moving signal to the unit, thereby moving the objective lens to a predetermined position.

Recording and reproducing device for pal video signal

Abstract: PURPOSE:To obtain an artificial burst signal with simple circuit constitution by adding a burst signal to a burst signal delayed by one horizontal period and by controlling an oscillator with the sum output. CONSTITUTION:Video signal PAL-V is inputted to BPF1, ACC circuit 2 and burst gate 3 and burst signal B is separated at gate 3. Signal B is supplied to 1H delay line 17, an input to and output from which are added by adder 21. The output of adder 21 is supplied via artificial burst gate 7 to crystal injection oscillator 22, from which a continuous artificial burst signal is obtained. Since a phase error can be reduced by operating oscillator 22 with the signal obtained by adding the input and output to and from delay line 17, the artificial burst signal of high precision can be obtained without using any APC circuit.

Phase synchronous oscillator

Abstract: PURPOSE:To prolong the free-running holding time without varying an output frequency even if an input signal is cut off, by providing a counter, D/A converter, adder, etc. CONSTITUTION:Phase difference detecting counter CNT6, D/A converter 7, adder 9, etc., are provided. Once input signal (a) is cut off, phase comparator 1 outputs a rectangular wave signal with a period twice that of output signal (b). On the other hand, a digital value stored in counter 6 is converted 7 into an analog value, which is applied via AND gate 8 to circuit, where it is added to the output of LPF2. Thus, circuit 9 outputs a voltage obtained by adding a control signal corresponding to a center frequency before voltage control osicllator VCX03 varies in characteristics to a signal corresponding to a stationary phase error after the characteristic change and before a self-scan, and the voltage is applied to oscillator 3 to control its oscillation frequency. Therefore, oscillator 3 is applied with the same voltage as before the free-running start and the oscillation frequency never changes, prolonging greatly the free-running holding time.

Minimum Parallel Binary Adders with NOR (NAND) Gates

Abstract: Parallel binary adders of n bits long in single-rail input logic which have a minimum number of NOR gates are derived in this paper. The minimality of the number of NOR gates is proved for an arbitrary value of n. Also, it is proved that the adders must be a cascade of basic modules and that there exist many different types of basic modules. These adders have fewer gates and shorter net gate delays (or fewer connections) than the widely used carry-ripple adders which are a cascade of one-bit full adders. Design procedures of such adders are described, based on the integer-programming logic design method. There are many solutions but adders with few connections and those with few net gate delays (all these adders have the minimum number of gates) are shown as important examples. Altbough these adders are designed with NOR gates, the results in this paper are applicable to adders with NAND gates by duality conversion.

Logic circuit arrangement in the integrated MOS-circuitry technique

Abstract: A multi-stage logic circuit employing integrated MOS-circuit techniques having gates to produce carry signals between stages where the gates which transfer the carry signals are designed as transfer-gates. Specific circuits are shown for full adders, comparators, synchronous binary counters, forwards-backwards synchronous binary counters and forwards-synchronous counting decades.

External data store memory device

Abstract: A device for use with a digital computer for storing standard software used by the computer and modifying the address portions of the standard software prior to transmission to the computer The device includes a ROM package containing a ROM within which is stored a standard software subprogram written assuming it is stored at an absolute location in the computer's memory other than its actual location in the computer's memory system Also included in the ROM package is a base register which can be loaded, under control of the operating system software, with an offset value reflecting the difference between the actual starting memory system location of the subprogram stored in the ROM and the assumed absolute starting location of the subprogram Each ROM word includes an extra bit to indicate whether the corresponding data word contains an address requiring relocation As a word is read out of ROM, a gating circuit tests whether an address relocation is required If the test is positive, the gating circuit gates the value in the base register into one input of an adder located on the ROM package, the other input to the adder coming from the data word read out of the ROM The resulting modified data word outputted from the adder is sent to the computer If the ROM output does not indicate that a relocation is required, the gating circuit provides a zero input to the adder so that the adder output reflects the unmodified input from the ROM

Luminanceecolor separation system

Abstract: PURPOSE:To attain the luminance-color separation of a composite color television signal while maintaining high picture quality without losing original picture information. CONSTITUTION:A composite color television signal from input terminal 1 and a signal delayed by one frame period by frame memory 1 are both led to subtractor 2 to form a difference signal between the input and output signals of frame memory 1, so that the difference signal will be zero at the still-picture part and negative or positive in polarity at the motion-picture part. this difference signal is supplied to decision circuit 3, which extracts a motion decision signal. Adder 5 and subtracter 6, on the other hand, generate a sum signal and a differenc signal between the input and output composite color television signals of frame memory 1. Further, the signal from terminal 1 is supplied to delay line 4, whose input and output signals are supplied to adder 8 and subtracter 9, so that a sum signal and a difference signal between two scanning lines adjoining each other in the same field will be extracted as the luminance signal and carrier of the motion-picture part.

Dynamic frequency and time voice encryption system and method

Abstract: A voice scrambler system (10) for encryption of a voice signal is provided. The voice scrambler system (10) includes a first generator (124) for generating a fixed frequency signal. A second generator (132) is provided for generating a plurality of frequency signals. Control circuitry (134) is provided for dynamically controlling the second generator (132) for randomly generating the plurality of variable frequency signals. A mixer (122) heterodynes the voice signal with the fixed frequency signal generated by the first generator (124). A filter (126) filters the output of the first mixer (122). An adder (128) adds the voice signal and the output of the first filter (126). A second mixer (130) heterodynes the output of the adder (128) with one of the plurality of frequency signals generated by the second generator (132). A second filter (136) filters the output of the second mixer (130) to generate an encrypted voice signal.

Beam deflection method and apparatus for sector scan ultrasound imaging systems

Abstract: Beam deflection delay time data of (L×M) data bits are stored in a read-only memory from which each datum is retrieved successively when the ultrasound beam is deflected to a given angle and repeatedly accumulated in a digital adder through a latching circuit connected between the output and input of the adder, where L is the number of discrete steps of deflection angle and M is a binary number representing the total delay time of piezoelectric transducers. The successively latched data is distributed to respective programmable counters for presetting the count values thereof to store therein respective delay time data. High frequency count pulses are supplied to the counters after the latter has been preset for delivery of carry outputs to the associated piezoelectric transducers. Beam convergence delay time data is also stored in a second memory from which each datum is retrieved for each transducer element and accumulated so that a tapered configuration of binary differential numbers is created and added to the beam deflection delay time data for converging the ultrasound beam.

Arithmetic logic unit controller

Abstract: A high speed parallel digital adder includes a control circuit which is the subject of this invention The control circuit is a single integrated circuit having: add/subtract select logic for selecting the addition and subtraction functions of the adder; a one's complement carry look ahead logic unit for generating carry look ahead signals; and a logic unit for generating the sign of the resultant of the two operands, a complement data output, the underflow, and the overflow

Colour TV camera parabolic stray light component compensation - adding parabolic signal, whose amplitude is controlled by mean video level, to video signal

Abstract: The parabolic component of stray light in colour TV cameras is compensated. A parabolic compensation signal whose amplitude is controlled by the mean value of the video signal is added to the main input signal. The object is to minimise any stray light and distortion of the black level due to non-uniform reflexion from signal electrodes, vignetting, and also infrared sources. The main video signal is fed to one input of an adder (2) and to a mean value forming circuit (3) whose output is multiplied (8) by a parabolic signal (9). The output of the multiplier feeds the other input of the adder (2).

Signal converting circuit

Abstract: PURPOSE:To omit the complicated delay circuit and thus simplify the circuit constitution, by obtaining the frequency characteristics difference of two signals via the filter having the minimum phase transition and then approximating the characteristics difference to the transmission characteristics covering from the sound source in the sound field to the listener's ears CONSTITUTION:Input signals Ri and Li supplied from input terminals 1 and 2 are applied to the input terminals of adder 22 and subtractor 23 each The subtraction result of subtractor 23 is applied to circuit 26 which possesses the fixed amplitude frequency characteristics only through the filter having the minimum phase transition and via phase-shift circuit 24 And the addition result of adder 22 is applied to circuit 25 which is formed so as to possess the fixed amplitude frequency characteristics through the filter having the minimum phase transition The frequency characteristics difference between circuits 25 and 26 is made to approximate to the result obtained through the calculation based on the transmission characteristics ranging from the sound source in the sound field to the listener's ears and in relation to the fixed position aimed for the reproduction state of the output of the signal converting circuit As a result, the constitution can be simplified for the signal converting circuit and with no installation of the complicated delay circuit