Showing papers on "Adder published in 1993"

A reduced-area scheme for carry-select adders

Abstract: The carry-select or conditional-sum adders require carry-chain evaluations for each block for both the values of block-carry-in, 0 and 1. The author introduces a scheme to generate carry bits with block-carry-in 1 from the carries of a block with block-carry-in 0. This scheme is then applied to carry-select and parallel-prefix adders to derive a more area-efficient implementation for both the cases. The proposed carry-select scheme is assessed relative to carry-ripple, classical carry-select, and carry-skip adders. The analytic evaluation is done with respect to the gate-count model for area and gate-delay units for time. >

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic

Abstract: Describes circuit techniques for fabricating a high-speed adder using pass-transistor logic. Double pass-transistor logic (DPL) is shown to improve circuit performance at reduced supply voltage. Its symmetrical arrangement and double-transmission characteristics improve the gate speed without increasing the input capacitance. A carry propagation circuit technique called conditional carry selection (CCS) is shown to resolve the problem of series-connected pass transistors in the carry propagation path. By combining these techniques, the addition time of a 32-b ALU can be reduced by 30% from that of an ordinary CMOS ALU. A 32-b ALU test chip is fabricated in 0.25- mu m CMOS technology using these circuit techniques and is capable of an addition time of 1.5 ns at a supply voltage of 2.5 V. >

Check image capture system

Abstract: A check image capture system processes on-us and transit checks to achieve significant cost savings and efficiencies. The check image capture system includes an image pickup device 30, teller personal computer 32, check amount encoder 34, and check amount adder 36. Checks presented to the teller are scanned by the image pickup device 30, which forms image data representing respective images of the checks. Each check is then classified as an on-us check or a transit check. Transit checks are transported to the amount encoder 34 whereas on-us checks are truncated. The check amount adder 36 receives amount data for the transit checks and computes the total of the transit check amounts. The check amount encoder encodes each transit check with the amount associated therewith if the check amount total is correct. The computer is programmed to store the image data and to identify and store account number data, bank number data, and check number data associated with the checks, and to provide the amount data associated with the transit checks to the check amount adder.

M*N Booth encoded multiplier generator using optimized Wallace trees

Abstract: The architecture of a design method for an M-bit by N-bit Booth encoded parallel multiplier generator are discussed. An algorithm for reducing the delay inside the branches of the Wallace tree section is explained. The final step of adding two N+or-M-1-bit numbers is done by an optimal carry select adder stage. The algorithm for optimal partitioning of the N+or-M-1-bit adder is also presented. >

Efficient implementations of self-checking adders and ALUs

Abstract: The author presents efficient self-checking implementations for adders and ALUs (ripple carry, carry lookahead, carry skip schemes). Among all the known self-checking adders and ALUs the parity prediction scheme has the advantage to require the minimum overhead for the adder/ALU and the minimum overhead for the other data path blocks. It has also the advantage to be compatible with memory systems checked by parity codes. The drawback of this scheme is that it is not fault secure even for single stuck-at faults. The new designs require lower overhead than the above scheme and also they have all the other advantages of this scheme. In addition the new schemes are strongly fault secure or totally self-checking for a comprehensive fault model which includes stuck-at, stuck-on and stuck open faults. Thus, the new schemes are substantially better than any other known scheme.

Test responses compaction in accumulators with rotate carry adders

Abstract: An accumulator-based compaction (ABC) scheme for parallel compaction of test responses is presented. In this scheme an accumulator with an n-bit binary adder is slightly modified such that the quality of compaction defined by the asymptotic coverage drop is similar to that offered by shift registers with irreducible polynomials of cellular automata. A Markov-chain model is used to analyze both the asymptotic coverage drop introduced by this scheme, and its transient behavior. It is shown that the asymptotic coverage drop depends both on the size of the accumulator and the probability of a fault injection. The upper bound of the coverage drop during the transition phrase is also provided. The proposed scheme is compatible with the width of the data path, and the test can be applied at the normal mode speed. The minimal hardware overhead involves only one-bit register to implement the feedback between the carry-out and carry-in lines. >

An area/time-efficient motion estimation micro core

Abstract: An efficient microarchitecture for motion estimation is proposed. It achieves better time and area performance than the existing structures. Through pipelining and effective manipulation of two's-complement arithmetic, the adder complexity is kept to its lowest, while speed for a combined subtraction, absolution, and accumulation operation is made as fast as a carry-save addition. Together with a new DCT (discrete cosine transform) algorithm, the microstructure is further expanded and tailored to facilitate efficient execution of other video operations, such as DCT and filtering operations. >

Look up table implementation of fast carry for adders and counters

Abstract: Look up tables for use in programmable logic devices are modified to facilitate use of those tables to provide adders (including subtracters) and various types of counters. Each look up table is effectively partitioned into smaller look up tables when an adder or counter is required. One portion of the partitioned table is used to provide a sum out signal, while the other portion of the partitioned table is used to provide a fast carry out signal for application to the next stage of the adder or counter.

Digital adder and method for adding 64-bit, 16-bit and 8-bit words

Abstract: An adder for a 64-bit microprocessor which has three modes of operations, specifically, a 64-bit mode, a second mode where the adder in effect is four 16-bit adders and a third mode where the adder is, in effect, eight 8-bit adders. Two levels of Kogge-Stone trees are used, the first to generate group carries and propagate signals and the second for generating the carry signals for the 64-bit case. In the case of the 8-bit and 16-bit modes, the second level Kogge-Stone tree is not used, rather ordinary logic generates the appropriate carries. Exclusive ORing for conditional sums is performed in parallel with the generation of the carry signals.

Accumulator-based compaction of test responses

Abstract: An accumulator-based compaction (ABC) scheme for parallel compaction of test responses is introduced. The asymptotic and transient coverage drop introduced by accumulators with binary and 1's complement adders is studied using Markov chain models. It is proven that the asymptotic coverage drop in ABC with binary adders is 2/sup -k/, where k is the number of bits in the adder that the fault can reach. In ABC with 1's complement adders, the asymptotic coverage drop for a fairly general class of faults is (2n-1)/sup -1/, where n is the total number of bits. The analysis of transient behavior relates the coverage drop with the probability of fault injection, the size of the accumulator, and the length of the test experiment. The process is characterized by damping factors derived for various values of these parameters. >

Reduced area multipliers

Abstract: As developed by Wallace (1964) and Dadda (1965), a high-speed method for the parallel multiplication of two binary numbers is to reduce their partial products to two numbers whose sum is equal to the product. The resulting two numbers are then summed using a fast carry-propagate adder. The authors present a multiplier, the reduced area multiplier, with a novel reduction scheme which results in fewer components and less interconnect overhead than either Wallace or Dadda multipliers. This reduction scheme is especially useful for pipelined multipliers, because it minimizes the number of latches required in the reduction of the partial products. Equations are given for determining the number of components and a method is presented for estimating the interconnect overhead for Wallace, Dadda and reduced area multipliers. Area estimates indicate that pipelined reduced area multipliers require 3 to 8% less area than equivalent Wallace multipliers and 15 to 25% less area than equivalent Dadda multipliers. >

Split multiply operation

Abstract: A multiplier (220) selectively multiplies either a pair of 2N bit digital numbers or two pair of N bit digital numbers. The multiplier (220) includes a first input encoding circuit (350), a second input encoding circuit (352), a number of partial product generators (353, 354, 356, 363, 364, 366) and a set of adders (355, 357, 365, 367, 368, 369). The first input encoder circuit (350) generates partial product control signals from a first data word holding either a first 2N bit number or a first pair of N bit numbers. The second input encoding circuit (352) generates partial product input signals to the partial product generators (353, 354, 356, 363, 364, 366) from a second data word holding either a second 2N bit number or a second pair of N bit numbers. A first set of adders (355, 357) forms a weighted first sum of the first set of partial products signals. A second set of adders (365, 367) forms a weighted second sum of said second set of partial product signals. A third adder ( 368) forms a weighted sum of the first and second sums. The multiplexer (369) forms an output from the third adder in the 2N by 2N multiplication mode and forms an output having least significant bits corresponding to the first sum and most significant bits corresponding to the second sum in the pair of N by N multiplications modes.

Diversity radio receiver

Abstract: A plurality of reception branches receive digital modulated signals and convert received digital modulated signals into intermediate frequency signals having frequency differences having a predetermined relationship with a modulation baseband signal. An adder adds the intermediate frequency signals converted by the plurality of reception branches. A delayed and differential detection section delays and differentially detects a sum signal from the adder. A post detection filter filters a delayed and differentially detected signal from the delayed and differential detection section at a bandwidth higher than a Nyquist frequency of the received digital modulated signals, thereby outputting demodulated signals of the received digital modulated signals.

Novel parallel architectures for short-time Fourier transform

Abstract: Novel parallel architectures for the short-time Fourier transform based on adaptive time-recursive processing is proposed for efficient VLSI implementation. Only one multiplier and one adder are required. The approach can be easily extended to multidimensional cases without the transpose operation. Various properties of the proposed architectures are presented. >

A recursive carry-lookahead/carry-select hybrid adder

Abstract: The author presents a very fast adder for double-precision mantissas, which is an improvement on T. Lynch and E. E. Swartzlandes, Jr.'s spanning tree carry lookahead adder or redundant cell adder (see ibid., vol. 41, 1992) which was implemented using the Am29050 microprocessor. The adder presented is faster than theirs mainly because Manchester carry chains of various lengths are used instead of chains all of the same length. >

Interlock collapsing ALU's

Abstract: A device capable of executing interlocked fixed point arithmetic logic unit (ALU) instructions in parallel with other instructions causing the execution interlock is presented. The device incorporates the design of a 3-1 ALU and can execute two's complement, unsigned binary, and binary logical operations. It is shown that status for ALU operations using a 3-1 ALU can be determined in a parallel fashion, resulting in the compliance of the proposed device with predetermined architectural behavior of single instruction execution. The device requires no more logic stages than does a 3-1 binary adder using a carry-save adder (CSA) followed by a carry-lookahead adder (CLA) design. Design considerations using a commonly available CMOS technology are also reported, indicating that the device will not increase the machine cycle of an implementation. It is suggested that the device can maintain full architectural compatibility. >

Design and application of pipelined dynamic CMOS ternary logic and simple ternary differential logic

Abstract: Dynamic CMOS ternary logic circuits that can be used to form a pipelined system with nonoverlapped two-phase clocks are proposed and investigated. The proposed dynamic ternary gates do not dissipate DC power and have full voltage swings. A circuit structure called the simple ternary differential logic (STDL) is also proposed and analyzed, and an optimal procedure is developed. An experimental chip has been fabricated in a 1.2- mu m CMOS process and tested. A binary pipelined multiplier has been designed, using the proposed dynamic ternary logic circuits in the interior of the multiplier for coding of radix-2 redundant positive-digit number. The structure has the advantages of higher operating frequency, less latency, and lower device count as compared with the conventional binary parallel pipelined multiplier. The advantages of the circuits over other dynamic ternary logic circuits are shown. >

Designing optimum one-level carry-skip adders

Abstract: The author shows how to design one-level carry-skip adders that attain very high speeds. One-level carry-skip adders are very fast adders that are hardly more complex than the much-slower ripple adders. The design procedure allows the use of realistic component delays obtained by simulation and is technology-independent. An example of a 64-b, 1 mu m CMOS adder is given. This adder achieves an add time of 6.23 ns, measured by SPICE simulation with realistic loads. This delay figure excludes sum buffering delays, which depend on the particular application of the adder. The combination of high-speed and simplicity makes one-level carry-skip adders attractive for applications in highly parallel systems. >

A 10-b 100-Msample/s pipelined subranging BiCMOS ADC

Abstract: The authors describe a 10-b, 100-Ms/s ADC (analog-to-digital converter) with a pipelined subranging scheme, a sample-and-hold amplifier with 7.6-ns acquisition time, and a 94-dB, 335-MHz op amp, enabling it to operate with 950-mW power dissipation from a single -5 V power supply. The design consists of sample-and-hold amplifiers, a coarse 6-b flash ADC, a fine 5-b flash ADC, a digital-to-analog converter, an analog subtractor, a register, and a digital adder with an error-correction function. The ADC is fabricated using a 0.8- mu m BiCMOS process featuring a double-layer polysilicon capacitor. The signal-to-noise-plus-distortion ratio as a function of input frequency at a 100-Ms/s conversion rate is shown. >

Perishable good integrity indicator

Abstract: A perishable good integrity indicator includes a first oscillator for outputting a first clock signal which does not substantially vary in response to temperature. A second oscillator outputs a second clock temperature which varies as a function of temperature. A counter counts the pulses of the second clock signal during a time period determined by the first clock and outputs a count value. A data table receives the count value, translates the count value into a time temperature value representing the relationship of time and temperature during the time period and outputs the time temperature value to an adder. The adder adds the time temperature values output by the data table over time and outputs a cumulative time temperature value corresponding to shelf life for a product.

Polarization-encoded optical logic operations in photorefractive media

Abstract: We propose and demonstrate optical logic operations using polarization encoding and wave mixing in photorefractive crystals. In our approach two orthogonal polarization states of light beams are used to represent respective logic values of 1 and 0. All 16 two-input logic operations can be easily achieved by use of the recording and readout of photoinduced volume gratings in photorefractive crystals. An optical full adder is also proposed and demonstrated.

Estimating the power consumption of CMOS adders

Abstract: Six types of adders are examined in an attempt to model their power dissipation. It is shown that the use of a relatively simple model provides results that are qualitatively accurate, when compared to more sophisticated models and to physical implementations of the circuits. The main discrepancy between the simple model and the physical measurements seems to be the assumption that all gates will consume the same amount of power when they switch, regardless of their fan-in or fanout. Because the carry lookahead adder has several gates with a fan out and fan-in higher than two, the simple model underestimates its power dissipation. >

Arithmetical unit including accumulating operation

Abstract: An improved M-bit accumulator for increasing speed and reducing circuit size includes an N-bit (N

The HOL-Voss System: Model-Checking inside a General-Purpose Theorem-Prover

Abstract: We have extended the HOL theorem-prover with an efficient implementation of symbolic trajectory evaluation. Using this extension we can obtain verification results for models of digital hardware — usually with much less effort than would be required using a conventional interactive theorem-proving approach. We illustrate the use of this extension with three examples, namely, the formal verification of a 32-bit adder, an 8-bit by 8-bit multiplier and the MAJORLOGIC block of the Viper microprocessor.

Efficient hardware handling of positive and negative overflow resulting from arithmetic operations

Abstract: A computer system provides handling of positive and negative overflow. A first arithmetic operation is performed on a first n-bit unsigned binary operand and a second n-bit signed binary operand to produce an n-bit unsigned binary result. Overflow detection logic circuitry within the arithmetic logic unit detects positive overflow or negative overflow resulting from the arithmetic operation. When there is a positive overflow, saturation logic replaces the output of the two's complement adder with a value of 2 n-1 . When there is a negative overflow, the saturation logic replaces the output of the two's complement adder with a value of 0. In an alternate embodiment, a first arithmetic operation is performed on a first n-bit signed binary operand and a second n-bit signed binary operand to produce an n-bit positive signed binary result. For example the arithmetic operation is an addition or subtraction performed by a two's complement adder. In the alternate embodiment, overflow detection logic circuitry within the arithmetic logic unit detects positive overflow or negative overflow resulting from the arithmetic operation. When there is a positive overflow, saturation logic replaces the output of the two's complement adder with a value of 2 n-1 -1. When there is a negative overflow, the saturation logic replaces the output of the two's complement adder with a value of 0.

A 17 /spl times/ 69 bit multiply and add unit with redundant binary feedback and single cycle latency

Abstract: The authors describe a numeric processor with a kernel that is a tree of redundant binary adders and effects either a 17 /spl times/ 69-b multiply-and-add or a 19 /spl times/ 69-b multiply with exact redundant binary output and single cycle latency. Feedback paths selectively allow a high-order or low-order part of the adder tree output to be fed back in redundant binary form to the multiplicand and/or addend inputs to the adder tree. The authors describe algorithms iteratively using this adder tree kernel for IEEE double extended multiplication, division, and square root; conversions between 18-digit BCD integers and 64-b binary integers; and transcendental function evaluation. The multiplier design described was implemented in the Cyrix 83D87 numeric coprocessor (typically 33 MHz). Results for this coprocessor as compared with competitive x87 units are included. >

Result normalizer and method of operation

Abstract: A result normalizer (58) for use with an adder (56) generates a mask in two stages that indicates the location of the leading one in the adder result. In the first stage, a leading zero anticipator (68) determines the position to within two digits. In the second stage, a count leading zero indicator (70) determines the position to a single digit. The mask is used to control the number of digits that each stage of a multiplexer array (66) shifts the adder result. The output of the multiplexer array thereby contains a leading one. The result normalizer may be advantageously used in high performance applications such as in a floating point execution unit in a data processor or in digital signal processing systems.

Data processor a method and apparatus for performing postnormalization in a floating-point execution unit

Abstract: A method and apparatus for performing prenormalization during execution by an execution unit (100) of a floating-point add/subtract operation using two data operands. The execution unit (100) adds a mantissa portion of a first and a second floating-point data operand to generate a prenormalized mantissa sum. The execution unit (100) minimizes critical path delays to allow high-performance floating-point calculations while simultaneously reducing logic. Instead of treating the prenormalized mantissa sum as a 64-bit value with special treatment in case of a carry out due to overflow, the floating-point adder 100 treats the prenormalized mantissa sum as a 65-bit value, with the most significant bit being a carry output. Instead of conditionally incrementing an initial exponent value, the initial exponent value is always incremented. Thus, allowing the floating-point adder unit 100 to perform the exponent adjustments for normalization and for rounding faster.

Multiple-valued logic computation circuits using micro- and nanoelectronic devices

Abstract: The advantages of the negative transconductance of the resonant tunneling transistor (RTT) for implementing very efficient multivalued-logic (MVL) arithmetic building blocks are examined. Full adders are described for both the positive-digit 2.4 redundant number system and the signed-digit 4.3 minimum-redundant number system. The outlook for nanoelectronic MVL is considered. >

A BiCMOS dynamic carry lookahead adder circuit for VLSI implementation of high-speed arithmetic unit

Abstract: A BiCMOS dynamic carry lookahead circuit that is free from race problems is presented. A 16 b full-adder test circuit, which has been designed based on a 2 mu m BiCMOS technology, shows a more than five times improvement in speed as compared to the CMOS Manchester carry lookahead (MCLA) circuit. The speed advantage of the BiCMOS dynamic carry lookahead circuit is even greater in a 32- or 64-b adder. >